Tom Warren 722e000ccd Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc. ... Added PLL variables (dividers mask/shift, lock enable/detect, etc.) to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X. Used pllinfo struct in all clock functions, validated on T210. Should be equivalent to prior code on T124/114/30/20. Thanks to Marcel Ziswiler for corrections to the T20/T30 values. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>		2015-08-05 15:22:51 -07:00
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clock.c	Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.	2015-08-05 15:22:51 -07:00
funcmux.c	ARM: Tegra210: Add SoC code/include files for T210	2015-07-28 10:30:19 -07:00
Kconfig	T210: Add support for 64-bit T210-based P2571 board	2015-07-28 10:30:20 -07:00
Makefile	ARM: Tegra210: Add SoC code/include files for T210	2015-07-28 10:30:19 -07:00
pinmux.c	ARM: tegra: pinctrl: move Tegra210 code to the correct dir	2015-03-30 09:54:06 -07:00
xusb-padctl.c	ARM: Tegra210: Add SoC code/include files for T210	2015-07-28 10:30:19 -07:00