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88b697fb37
Not all "periph" clocks are children of the AHB clock, some have the AXI
clock as their parent & the mtimer clock is derived from the external
reference clock directly. Stop assuming the AHB clock to be the parent
of all "periph" clocks and define their correct parents instead.
Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
48 lines
1.6 KiB
C
48 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2020 Microchip Technology Inc.
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* Padmarao Begari <padmarao.begari@microchip.com>
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*/
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#ifndef __MICROCHIP_MPFS_CLK_H
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#define __MICROCHIP_MPFS_CLK_H
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#include <linux/clk-provider.h>
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/**
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* mpfs_clk_register_cfgs() - register configuration clocks
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*
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* @base: base address of the mpfs system register.
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* @parent: a pointer to parent clock.
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* Return: zero on success, or a negative error code.
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*/
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int mpfs_clk_register_cfgs(void __iomem *base, struct clk *parent);
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/**
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* mpfs_clk_register_msspll() - register the mss pll
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*
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* @base: base address of the mpfs system register.
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* @parent: a pointer to parent clock.
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* Return: zero on success, or a negative error code.
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*/
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int mpfs_clk_register_msspll(void __iomem *base, struct clk *parent);
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/**
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* mpfs_clk_register_periphs() - register peripheral clocks
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*
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* @base: base address of the mpfs system register.
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* @dev: udevice representing the clock controller.
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* Return: zero on success, or a negative error code.
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*/
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int mpfs_clk_register_periphs(void __iomem *base, struct udevice *dev);
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/**
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* divider_get_val() - get the clock divider value
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*
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* @rate: requested clock rate.
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* @parent_rate: parent clock rate.
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* @table: a pointer to clock divider table.
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* @width: width of the divider bit field.
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* @flags: common clock framework flags.
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* Return: divider value on success, or a negative error code.
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*/
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int divider_get_val(unsigned long rate, unsigned long parent_rate,
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const struct clk_div_table *table,
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u8 width, unsigned long flags);
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#endif /* __MICROCHIP_MPFS_CLK_H */
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