Sebastian Reichel 717bf50f4b board: ge: bx50v3: cleanup phy config ... The current PHY rework does the following things: 1. Configure 125MHz clock 2. Setup the TX clock delay (RX is enabled by default), 3. Setup reserved bits to avoid voltage peak The clock delays are nowadays already configured by the PHY driver (in ar803x_delay_config). The code for that can simply be dropped. The clock speed can also be configured by the PHY driver by adding the device tree property "qca,clk-out-frequency". What is left is setting up the undocumented reserved bits to avoid the voltage peak problem. I slightly improved its documentation while updating the board's PHY rework code. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>		2020-12-26 14:56:09 +01:00
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arc	spi: dw: Add SoC-specific compatible strings	2020-12-18 16:16:37 +05:30
arm	board: ge: bx50v3: cleanup phy config	2020-12-26 14:56:09 +01:00
m68k	arch: Move NEEDS_MANUAL_RELOC symbol to Kconfig	2020-11-04 10:13:44 -05:00
microblaze	microblaze: Enable GCC garbage collector for full U-Boot	2020-11-20 10:42:53 +01:00
mips	spi: dw: Add SoC-specific compatible strings	2020-12-18 16:16:37 +05:30
nds32	treewide: convert bd_t to struct bd_info by coccinelle	2020-07-17 09:30:13 -04:00
nios2	cpu: Convert the methods to use a const udevice *	2020-07-25 14:46:57 -06:00
powerpc	powerpc: mpc85xx: Allow boards to override CONFIG_USB_MAX_CONTROLLER_COUNT	2020-12-10 13:56:39 +05:30
riscv	riscv: Add device tree bindings for SPI	2020-12-18 16:16:37 +05:30
sandbox	patman status subcommand to collect tags from Patchwork	2020-11-06 11:27:14 -05:00
sh	sh: r2dplus: Add SCIF1 to the basic DT	2020-08-02 19:58:27 +02:00
x86	fsp: Move and rename fsp_types.h file	2020-12-22 10:19:40 +08:00
xtensa	xtensa: Remove arch_setup_bdinfo()	2020-08-26 09:19:40 +02:00
.gitignore
Kconfig	patman status subcommand to collect tags from Patchwork	2020-11-06 11:27:14 -05:00
u-boot-elf.lds	arch: Add explicit linker script for u-boot-elf	2020-04-03 11:52:55 -04:00