mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 22:03:15 +00:00
843ed983a0
Some boards with the Allwinner F1C100s family SoCs use UART1 for its debug UART, so define the pins for the SPL and the pinmux name and mux value for U-Boot proper. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
898 lines
24 KiB
C
898 lines
24 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <clk.h>
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#include <dm.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <dm/pinctrl.h>
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#include <errno.h>
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#include <malloc.h>
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#include <asm/gpio.h>
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extern U_BOOT_DRIVER(gpio_sunxi);
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/*
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* This structure implements a simplified view of the possible pinmux settings:
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* Each mux value is assumed to be the same for a given function, across the
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* pins in each group (almost universally true, with same rare exceptions not
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* relevant to U-Boot), but also across different ports (not true in many
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* cases). We ignore the first problem, and work around the latter by just
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* supporting one particular port for a each function. This works fine for all
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* board configurations so far. If this would need to be revisited, we could
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* add a "u8 port;" below and match that, with 0 encoding the "don't care" case.
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*/
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struct sunxi_pinctrl_function {
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const char name[sizeof("gpio_out")];
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u8 mux;
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};
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struct sunxi_pinctrl_desc {
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const struct sunxi_pinctrl_function *functions;
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u8 num_functions;
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u8 first_bank;
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u8 num_banks;
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};
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struct sunxi_pinctrl_plat {
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struct sunxi_gpio __iomem *base;
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};
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static int sunxi_pinctrl_get_pins_count(struct udevice *dev)
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{
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const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev);
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return desc->num_banks * SUNXI_GPIOS_PER_BANK;
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}
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static const char *sunxi_pinctrl_get_pin_name(struct udevice *dev,
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uint pin_selector)
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{
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const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev);
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static char pin_name[sizeof("PN31")];
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snprintf(pin_name, sizeof(pin_name), "P%c%d",
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pin_selector / SUNXI_GPIOS_PER_BANK + desc->first_bank + 'A',
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pin_selector % SUNXI_GPIOS_PER_BANK);
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return pin_name;
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}
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static int sunxi_pinctrl_get_functions_count(struct udevice *dev)
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{
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const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev);
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return desc->num_functions;
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}
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static const char *sunxi_pinctrl_get_function_name(struct udevice *dev,
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uint func_selector)
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{
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const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev);
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return desc->functions[func_selector].name;
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}
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static int sunxi_pinctrl_pinmux_set(struct udevice *dev, uint pin_selector,
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uint func_selector)
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{
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const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev);
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struct sunxi_pinctrl_plat *plat = dev_get_plat(dev);
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int bank = pin_selector / SUNXI_GPIOS_PER_BANK;
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int pin = pin_selector % SUNXI_GPIOS_PER_BANK;
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debug("set mux: %-4s => %s (%d)\n",
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sunxi_pinctrl_get_pin_name(dev, pin_selector),
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sunxi_pinctrl_get_function_name(dev, func_selector),
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desc->functions[func_selector].mux);
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sunxi_gpio_set_cfgbank(plat->base + bank, pin,
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desc->functions[func_selector].mux);
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return 0;
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}
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static const struct pinconf_param sunxi_pinctrl_pinconf_params[] = {
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{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
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{ "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 2 },
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{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
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{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 10 },
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};
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static int sunxi_pinctrl_pinconf_set_pull(struct sunxi_pinctrl_plat *plat,
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uint bank, uint pin, uint bias)
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{
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struct sunxi_gpio *regs = &plat->base[bank];
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sunxi_gpio_set_pull_bank(regs, pin, bias);
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return 0;
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}
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static int sunxi_pinctrl_pinconf_set_drive(struct sunxi_pinctrl_plat *plat,
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uint bank, uint pin, uint drive)
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{
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struct sunxi_gpio *regs = &plat->base[bank];
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if (drive < 10 || drive > 40)
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return -EINVAL;
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/* Convert mA to the register value, rounding down. */
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sunxi_gpio_set_drv_bank(regs, pin, drive / 10 - 1);
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return 0;
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}
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static int sunxi_pinctrl_pinconf_set(struct udevice *dev, uint pin_selector,
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uint param, uint val)
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{
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struct sunxi_pinctrl_plat *plat = dev_get_plat(dev);
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int bank = pin_selector / SUNXI_GPIOS_PER_BANK;
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int pin = pin_selector % SUNXI_GPIOS_PER_BANK;
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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case PIN_CONFIG_BIAS_PULL_DOWN:
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case PIN_CONFIG_BIAS_PULL_UP:
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return sunxi_pinctrl_pinconf_set_pull(plat, bank, pin, val);
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case PIN_CONFIG_DRIVE_STRENGTH:
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return sunxi_pinctrl_pinconf_set_drive(plat, bank, pin, val);
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}
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return -EINVAL;
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}
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static int sunxi_pinctrl_get_pin_muxing(struct udevice *dev, uint pin_selector,
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char *buf, int size)
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{
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struct sunxi_pinctrl_plat *plat = dev_get_plat(dev);
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int bank = pin_selector / SUNXI_GPIOS_PER_BANK;
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int pin = pin_selector % SUNXI_GPIOS_PER_BANK;
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int mux = sunxi_gpio_get_cfgbank(plat->base + bank, pin);
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switch (mux) {
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case SUNXI_GPIO_INPUT:
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strlcpy(buf, "gpio input", size);
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break;
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case SUNXI_GPIO_OUTPUT:
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strlcpy(buf, "gpio output", size);
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break;
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case SUNXI_GPIO_DISABLE:
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strlcpy(buf, "disabled", size);
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break;
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default:
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snprintf(buf, size, "function %d", mux);
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break;
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}
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return 0;
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}
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static const struct pinctrl_ops sunxi_pinctrl_ops = {
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.get_pins_count = sunxi_pinctrl_get_pins_count,
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.get_pin_name = sunxi_pinctrl_get_pin_name,
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.get_functions_count = sunxi_pinctrl_get_functions_count,
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.get_function_name = sunxi_pinctrl_get_function_name,
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.pinmux_set = sunxi_pinctrl_pinmux_set,
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.pinconf_num_params = ARRAY_SIZE(sunxi_pinctrl_pinconf_params),
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.pinconf_params = sunxi_pinctrl_pinconf_params,
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.pinconf_set = sunxi_pinctrl_pinconf_set,
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.set_state = pinctrl_generic_set_state,
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.get_pin_muxing = sunxi_pinctrl_get_pin_muxing,
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};
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static int sunxi_pinctrl_bind(struct udevice *dev)
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{
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struct sunxi_pinctrl_plat *plat = dev_get_plat(dev);
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struct sunxi_pinctrl_desc *desc;
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struct sunxi_gpio_plat *gpio_plat;
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struct udevice *gpio_dev;
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int i, ret;
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desc = (void *)dev_get_driver_data(dev);
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if (!desc)
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return -EINVAL;
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dev_set_priv(dev, desc);
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plat->base = dev_read_addr_ptr(dev);
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ret = device_bind_driver_to_node(dev, "gpio_sunxi", dev->name,
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dev_ofnode(dev), &gpio_dev);
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if (ret)
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return ret;
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for (i = 0; i < desc->num_banks; ++i) {
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gpio_plat = malloc(sizeof(*gpio_plat));
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if (!gpio_plat)
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return -ENOMEM;
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gpio_plat->regs = plat->base + i;
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gpio_plat->bank_name[0] = 'P';
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gpio_plat->bank_name[1] = 'A' + desc->first_bank + i;
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gpio_plat->bank_name[2] = '\0';
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ret = device_bind(gpio_dev, DM_DRIVER_REF(gpio_sunxi),
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gpio_plat->bank_name, gpio_plat,
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ofnode_null(), NULL);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int sunxi_pinctrl_probe(struct udevice *dev)
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{
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struct clk *apb_clk;
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apb_clk = devm_clk_get(dev, "apb");
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if (!IS_ERR(apb_clk))
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clk_enable(apb_clk);
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return 0;
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}
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static const struct sunxi_pinctrl_function suniv_f1c100s_pinctrl_functions[] = {
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{ "gpio_in", 0 },
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{ "gpio_out", 1 },
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{ "i2c0", 3 }, /* PE11-PE12 */
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{ "i2c1", 3 }, /* PD5-PD6 */
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{ "mmc0", 2 }, /* PF0-PF5 */
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{ "mmc1", 3 }, /* PC0-PC2 */
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{ "spi0", 2 }, /* PC0-PC3 */
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#if IS_ENABLED(CONFIG_UART0_PORT_F)
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{ "uart0", 3 }, /* PF2-PF4 */
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#else
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{ "uart0", 5 }, /* PE0-PE1 */
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#endif
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{ "uart1", 5 }, /* PA0-PA3 */
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};
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static const struct sunxi_pinctrl_desc __maybe_unused suniv_f1c100s_pinctrl_desc = {
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.functions = suniv_f1c100s_pinctrl_functions,
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.num_functions = ARRAY_SIZE(suniv_f1c100s_pinctrl_functions),
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.first_bank = SUNXI_GPIO_A,
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.num_banks = 6,
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};
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static const struct sunxi_pinctrl_function sun4i_a10_pinctrl_functions[] = {
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{ "emac", 2 }, /* PA0-PA17 */
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{ "gpio_in", 0 },
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{ "gpio_out", 1 },
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{ "i2c0", 2 }, /* PB0-PB1 */
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{ "i2c1", 2 }, /* PB18-PB19 */
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{ "mmc0", 2 }, /* PF0-PF5 */
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#if IS_ENABLED(CONFIG_MMC1_PINS_PH)
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{ "mmc1", 5 }, /* PH22-PH27 */
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#else
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{ "mmc1", 4 }, /* PG0-PG5 */
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#endif
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{ "mmc2", 3 }, /* PC6-PC15 */
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{ "mmc3", 2 }, /* PI4-PI9 */
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{ "spi0", 3 }, /* PC0-PC2, PC23 */
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#if IS_ENABLED(CONFIG_UART0_PORT_F)
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{ "uart0", 4 }, /* PF2-PF4 */
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#else
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{ "uart0", 2 }, /* PB22-PB23 */
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#endif
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};
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static const struct sunxi_pinctrl_desc __maybe_unused sun4i_a10_pinctrl_desc = {
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.functions = sun4i_a10_pinctrl_functions,
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.num_functions = ARRAY_SIZE(sun4i_a10_pinctrl_functions),
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.first_bank = SUNXI_GPIO_A,
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.num_banks = 9,
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};
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static const struct sunxi_pinctrl_function sun5i_a13_pinctrl_functions[] = {
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{ "emac", 2 }, /* PA0-PA17 */
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{ "gpio_in", 0 },
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{ "gpio_out", 1 },
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{ "i2c0", 2 }, /* PB0-PB1 */
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{ "i2c1", 2 }, /* PB15-PB16 */
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{ "mmc0", 2 }, /* PF0-PF5 */
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{ "mmc1", 2 }, /* PG3-PG8 */
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{ "mmc2", 3 }, /* PC6-PC15 */
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{ "spi0", 3 }, /* PC0-PC3 */
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#if IS_ENABLED(CONFIG_UART0_PORT_F)
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{ "uart0", 4 }, /* PF2-PF4 */
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#else
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{ "uart0", 2 }, /* PB19-PB20 */
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#endif
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{ "uart1", 4 }, /* PG3-PG4 */
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};
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static const struct sunxi_pinctrl_desc __maybe_unused sun5i_a13_pinctrl_desc = {
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.functions = sun5i_a13_pinctrl_functions,
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.num_functions = ARRAY_SIZE(sun5i_a13_pinctrl_functions),
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.first_bank = SUNXI_GPIO_A,
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.num_banks = 7,
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};
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static const struct sunxi_pinctrl_function sun6i_a31_pinctrl_functions[] = {
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{ "gmac", 2 }, /* PA0-PA27 */
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{ "gpio_in", 0 },
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{ "gpio_out", 1 },
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{ "i2c0", 2 }, /* PH14-PH15 */
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{ "i2c1", 2 }, /* PH16-PH17 */
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{ "mmc0", 2 }, /* PF0-PF5 */
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{ "mmc1", 2 }, /* PG0-PG5 */
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{ "mmc2", 3 }, /* PC6-PC15, PC24 */
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{ "mmc3", 4 }, /* PC6-PC15, PC24 */
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{ "spi0", 3 }, /* PC0-PC2, PC27 */
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#if IS_ENABLED(CONFIG_UART0_PORT_F)
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{ "uart0", 3 }, /* PF2-PF4 */
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#else
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{ "uart0", 2 }, /* PH20-PH21 */
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#endif
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};
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static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_pinctrl_desc = {
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.functions = sun6i_a31_pinctrl_functions,
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.num_functions = ARRAY_SIZE(sun6i_a31_pinctrl_functions),
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.first_bank = SUNXI_GPIO_A,
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.num_banks = 8,
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};
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static const struct sunxi_pinctrl_function sun6i_a31_r_pinctrl_functions[] = {
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{ "gpio_in", 0 },
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{ "gpio_out", 1 },
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{ "s_i2c", 2 }, /* PL0-PL1 */
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{ "s_uart", 2 }, /* PL2-PL3 */
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};
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static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_r_pinctrl_desc = {
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.functions = sun6i_a31_r_pinctrl_functions,
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.num_functions = ARRAY_SIZE(sun6i_a31_r_pinctrl_functions),
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.first_bank = SUNXI_GPIO_L,
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.num_banks = 2,
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};
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static const struct sunxi_pinctrl_function sun7i_a20_pinctrl_functions[] = {
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{ "emac", 2 }, /* PA0-PA17 */
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{ "gmac", 5 }, /* PA0-PA17 */
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{ "gpio_in", 0 },
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{ "gpio_out", 1 },
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{ "i2c0", 2 }, /* PB0-PB1 */
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{ "i2c1", 2 }, /* PB18-PB19 */
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{ "mmc0", 2 }, /* PF0-PF5 */
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#if IS_ENABLED(CONFIG_MMC1_PINS_PH)
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{ "mmc1", 5 }, /* PH22-PH27 */
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#else
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{ "mmc1", 4 }, /* PG0-PG5 */
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#endif
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{ "mmc2", 3 }, /* PC5-PC15, PC24 */
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{ "spi0", 3 }, /* PC0-PC2, PC23 */
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#if IS_ENABLED(CONFIG_UART0_PORT_F)
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{ "uart0", 4 }, /* PF2-PF4 */
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#else
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{ "uart0", 2 }, /* PB22-PB23 */
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#endif
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};
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static const struct sunxi_pinctrl_desc __maybe_unused sun7i_a20_pinctrl_desc = {
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.functions = sun7i_a20_pinctrl_functions,
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.num_functions = ARRAY_SIZE(sun7i_a20_pinctrl_functions),
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.first_bank = SUNXI_GPIO_A,
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.num_banks = 9,
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};
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static const struct sunxi_pinctrl_function sun8i_a23_pinctrl_functions[] = {
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{ "gpio_in", 0 },
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{ "gpio_out", 1 },
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{ "i2c0", 2 }, /* PH2-PH3 */
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{ "i2c1", 2 }, /* PH4-PH5 */
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{ "mmc0", 2 }, /* PF0-PF5 */
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{ "mmc1", 2 }, /* PG0-PG5 */
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{ "mmc2", 3 }, /* PC5-PC16 */
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{ "spi0", 3 }, /* PC0-PC3 */
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#if IS_ENABLED(CONFIG_UART0_PORT_F)
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{ "uart0", 3 }, /* PF2-PF4 */
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#endif
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{ "uart1", 2 }, /* PG6-PG7 */
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{ "uart2", 2 }, /* PB0-PB1 */
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};
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static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a23_pinctrl_desc = {
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.functions = sun8i_a23_pinctrl_functions,
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.num_functions = ARRAY_SIZE(sun8i_a23_pinctrl_functions),
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.first_bank = SUNXI_GPIO_A,
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.num_banks = 8,
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};
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static const struct sunxi_pinctrl_function sun8i_a23_r_pinctrl_functions[] = {
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{ "gpio_in", 0 },
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{ "gpio_out", 1 },
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{ "s_i2c", 3 }, /* PL0-PL1 */
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{ "s_uart", 2 }, /* PL2-PL3 */
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};
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static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a23_r_pinctrl_desc = {
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.functions = sun8i_a23_r_pinctrl_functions,
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.num_functions = ARRAY_SIZE(sun8i_a23_r_pinctrl_functions),
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.first_bank = SUNXI_GPIO_L,
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.num_banks = 1,
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};
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static const struct sunxi_pinctrl_function sun8i_a33_pinctrl_functions[] = {
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{ "gpio_in", 0 },
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{ "gpio_out", 1 },
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{ "i2c0", 2 }, /* PH2-PH3 */
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{ "i2c1", 2 }, /* PH4-PH5 */
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{ "mmc0", 2 }, /* PF0-PF5 */
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{ "mmc1", 2 }, /* PG0-PG5 */
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{ "mmc2", 3 }, /* PC5-PC16 */
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{ "spi0", 3 }, /* PC0-PC3 */
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#if IS_ENABLED(CONFIG_UART0_PORT_F)
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{ "uart0", 3 }, /* PF2-PF4 */
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#else
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{ "uart0", 3 }, /* PB0-PB1 */
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#endif
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{ "uart1", 2 }, /* PG6-PG7 */
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{ "uart2", 2 }, /* PB0-PB1 */
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};
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static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a33_pinctrl_desc = {
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.functions = sun8i_a33_pinctrl_functions,
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.num_functions = ARRAY_SIZE(sun8i_a33_pinctrl_functions),
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.first_bank = SUNXI_GPIO_A,
|
|
.num_banks = 8,
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_function sun8i_a83t_pinctrl_functions[] = {
|
|
{ "gmac", 4 }, /* PD2-PD23 */
|
|
{ "gpio_in", 0 },
|
|
{ "gpio_out", 1 },
|
|
{ "i2c0", 2 }, /* PH0-PH1 */
|
|
{ "i2c1", 2 }, /* PH2-PH3 */
|
|
{ "mmc0", 2 }, /* PF0-PF5 */
|
|
{ "mmc1", 2 }, /* PG0-PG5 */
|
|
{ "mmc2", 3 }, /* PC5-PC16 */
|
|
{ "spi0", 3 }, /* PC0-PC3 */
|
|
#if IS_ENABLED(CONFIG_UART0_PORT_F)
|
|
{ "uart0", 3 }, /* PF2-PF4 */
|
|
#else
|
|
{ "uart0", 2 }, /* PB9-PB10 */
|
|
#endif
|
|
{ "uart1", 2 }, /* PG6-PG7 */
|
|
{ "uart2", 2 }, /* PB0-PB1 */
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a83t_pinctrl_desc = {
|
|
.functions = sun8i_a83t_pinctrl_functions,
|
|
.num_functions = ARRAY_SIZE(sun8i_a83t_pinctrl_functions),
|
|
.first_bank = SUNXI_GPIO_A,
|
|
.num_banks = 8,
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_function sun8i_a83t_r_pinctrl_functions[] = {
|
|
{ "gpio_in", 0 },
|
|
{ "gpio_out", 1 },
|
|
{ "s_i2c", 2 }, /* PL8-PL9 */
|
|
{ "s_uart", 2 }, /* PL2-PL3 */
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a83t_r_pinctrl_desc = {
|
|
.functions = sun8i_a83t_r_pinctrl_functions,
|
|
.num_functions = ARRAY_SIZE(sun8i_a83t_r_pinctrl_functions),
|
|
.first_bank = SUNXI_GPIO_L,
|
|
.num_banks = 1,
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_function sun8i_h3_pinctrl_functions[] = {
|
|
{ "emac", 2 }, /* PD0-PD17 */
|
|
{ "gpio_in", 0 },
|
|
{ "gpio_out", 1 },
|
|
{ "i2c0", 2 }, /* PA11-PA12 */
|
|
{ "i2c1", 3 }, /* PA18-PA19 */
|
|
{ "mmc0", 2 }, /* PF0-PF5 */
|
|
{ "mmc1", 2 }, /* PG0-PG5 */
|
|
{ "mmc2", 3 }, /* PC5-PC16 */
|
|
{ "spi0", 3 }, /* PC0-PC3 */
|
|
#if IS_ENABLED(CONFIG_UART0_PORT_F)
|
|
{ "uart0", 3 }, /* PF2-PF4 */
|
|
#else
|
|
{ "uart0", 2 }, /* PA4-PA5 */
|
|
#endif
|
|
{ "uart1", 2 }, /* PG6-PG7 */
|
|
{ "uart2", 2 }, /* PA0-PA1 */
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_desc __maybe_unused sun8i_h3_pinctrl_desc = {
|
|
.functions = sun8i_h3_pinctrl_functions,
|
|
.num_functions = ARRAY_SIZE(sun8i_h3_pinctrl_functions),
|
|
.first_bank = SUNXI_GPIO_A,
|
|
.num_banks = 7,
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_function sun8i_h3_r_pinctrl_functions[] = {
|
|
{ "gpio_in", 0 },
|
|
{ "gpio_out", 1 },
|
|
{ "s_i2c", 2 }, /* PL0-PL1 */
|
|
{ "s_uart", 2 }, /* PL2-PL3 */
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_desc __maybe_unused sun8i_h3_r_pinctrl_desc = {
|
|
.functions = sun8i_h3_r_pinctrl_functions,
|
|
.num_functions = ARRAY_SIZE(sun8i_h3_r_pinctrl_functions),
|
|
.first_bank = SUNXI_GPIO_L,
|
|
.num_banks = 1,
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_function sun8i_v3s_pinctrl_functions[] = {
|
|
{ "emac", 4 }, /* PD0-PD17 */
|
|
{ "gpio_in", 0 },
|
|
{ "gpio_out", 1 },
|
|
{ "i2c0", 2 }, /* PB6-PB7 */
|
|
{ "i2c1", 2 }, /* PB8-PB9 */
|
|
{ "mmc0", 2 }, /* PF0-PF5 */
|
|
{ "mmc1", 2 }, /* PG0-PG5 */
|
|
{ "mmc2", 2 }, /* PC0-PC10 */
|
|
{ "spi0", 3 }, /* PC0-PC3 */
|
|
#if IS_ENABLED(CONFIG_UART0_PORT_F)
|
|
{ "uart0", 3 }, /* PF2-PF4 */
|
|
#else
|
|
{ "uart0", 3 }, /* PB8-PB9 */
|
|
#endif
|
|
{ "uart1", 2 }, /* PG6-PG7 */
|
|
{ "uart2", 2 }, /* PB0-PB1 */
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_desc __maybe_unused sun8i_v3s_pinctrl_desc = {
|
|
.functions = sun8i_v3s_pinctrl_functions,
|
|
.num_functions = ARRAY_SIZE(sun8i_v3s_pinctrl_functions),
|
|
.first_bank = SUNXI_GPIO_A,
|
|
.num_banks = 7,
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_function sun9i_a80_pinctrl_functions[] = {
|
|
{ "gmac", 2 }, /* PA0-PA17 */
|
|
{ "gpio_in", 0 },
|
|
{ "gpio_out", 1 },
|
|
{ "i2c0", 2 }, /* PH0-PH1 */
|
|
{ "i2c1", 2 }, /* PH2-PH3 */
|
|
{ "mmc0", 2 }, /* PF0-PF5 */
|
|
{ "mmc1", 2 }, /* PG0-PG5 */
|
|
{ "mmc2", 3 }, /* PC6-PC16 */
|
|
{ "spi0", 3 }, /* PC0-PC2, PC19 */
|
|
#if IS_ENABLED(CONFIG_UART0_PORT_F)
|
|
{ "uart0", 4 }, /* PF2-PF4 */
|
|
#else
|
|
{ "uart0", 2 }, /* PH12-PH13 */
|
|
#endif
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_pinctrl_desc = {
|
|
.functions = sun9i_a80_pinctrl_functions,
|
|
.num_functions = ARRAY_SIZE(sun9i_a80_pinctrl_functions),
|
|
.first_bank = SUNXI_GPIO_A,
|
|
.num_banks = 8,
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_function sun9i_a80_r_pinctrl_functions[] = {
|
|
{ "gpio_in", 0 },
|
|
{ "gpio_out", 1 },
|
|
{ "s_i2c0", 2 }, /* PN0-PN1 */
|
|
{ "s_i2c1", 3 }, /* PM8-PM9 */
|
|
{ "s_uart", 3 }, /* PL0-PL1 */
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_r_pinctrl_desc = {
|
|
.functions = sun9i_a80_r_pinctrl_functions,
|
|
.num_functions = ARRAY_SIZE(sun9i_a80_r_pinctrl_functions),
|
|
.first_bank = SUNXI_GPIO_L,
|
|
.num_banks = 3,
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = {
|
|
{ "emac", 4 }, /* PD8-PD23 */
|
|
{ "gpio_in", 0 },
|
|
{ "gpio_out", 1 },
|
|
{ "i2c0", 2 }, /* PH0-PH1 */
|
|
{ "i2c1", 2 }, /* PH2-PH3 */
|
|
{ "mmc0", 2 }, /* PF0-PF5 */
|
|
{ "mmc1", 2 }, /* PG0-PG5 */
|
|
{ "mmc2", 3 }, /* PC1-PC16 */
|
|
{ "pwm", 2 }, /* PD22 */
|
|
{ "spi0", 4 }, /* PC0-PC3 */
|
|
#if IS_ENABLED(CONFIG_UART0_PORT_F)
|
|
{ "uart0", 3 }, /* PF2-PF4 */
|
|
#else
|
|
{ "uart0", 4 }, /* PB8-PB9 */
|
|
#endif
|
|
{ "uart1", 2 }, /* PG6-PG7 */
|
|
{ "uart2", 2 }, /* PB0-PB1 */
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a64_pinctrl_desc = {
|
|
.functions = sun50i_a64_pinctrl_functions,
|
|
.num_functions = ARRAY_SIZE(sun50i_a64_pinctrl_functions),
|
|
.first_bank = SUNXI_GPIO_A,
|
|
.num_banks = 8,
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_function sun50i_a64_r_pinctrl_functions[] = {
|
|
{ "gpio_in", 0 },
|
|
{ "gpio_out", 1 },
|
|
{ "s_i2c", 2 }, /* PL8-PL9 */
|
|
{ "s_uart", 2 }, /* PL2-PL3 */
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a64_r_pinctrl_desc = {
|
|
.functions = sun50i_a64_r_pinctrl_functions,
|
|
.num_functions = ARRAY_SIZE(sun50i_a64_r_pinctrl_functions),
|
|
.first_bank = SUNXI_GPIO_L,
|
|
.num_banks = 1,
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_function sun50i_h5_pinctrl_functions[] = {
|
|
{ "emac", 2 }, /* PD0-PD17 */
|
|
{ "gpio_in", 0 },
|
|
{ "gpio_out", 1 },
|
|
{ "i2c0", 2 }, /* PA11-PA12 */
|
|
{ "i2c1", 3 }, /* PA18-PA19 */
|
|
{ "mmc0", 2 }, /* PF0-PF5 */
|
|
{ "mmc1", 2 }, /* PG0-PG5 */
|
|
{ "mmc2", 3 }, /* PC1-PC16 */
|
|
{ "spi0", 3 }, /* PC0-PC3 */
|
|
#if IS_ENABLED(CONFIG_UART0_PORT_F)
|
|
{ "uart0", 3 }, /* PF2-PF4 */
|
|
#else
|
|
{ "uart0", 2 }, /* PA4-PA5 */
|
|
#endif
|
|
{ "uart1", 2 }, /* PG6-PG7 */
|
|
{ "uart2", 2 }, /* PA0-PA1 */
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h5_pinctrl_desc = {
|
|
.functions = sun50i_h5_pinctrl_functions,
|
|
.num_functions = ARRAY_SIZE(sun50i_h5_pinctrl_functions),
|
|
.first_bank = SUNXI_GPIO_A,
|
|
.num_banks = 7,
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_function sun50i_h6_pinctrl_functions[] = {
|
|
{ "emac", 5 }, /* PD0-PD20 */
|
|
{ "gpio_in", 0 },
|
|
{ "gpio_out", 1 },
|
|
{ "i2c0", 2 }, /* PD25-PD26 */
|
|
{ "i2c1", 4 }, /* PH5-PH6 */
|
|
{ "mmc0", 2 }, /* PF0-PF5 */
|
|
{ "mmc1", 2 }, /* PG0-PG5 */
|
|
{ "mmc2", 3 }, /* PC1-PC14 */
|
|
{ "spi0", 4 }, /* PC0-PC7 */
|
|
#if IS_ENABLED(CONFIG_UART0_PORT_F)
|
|
{ "uart0", 3 }, /* PF2-PF4 */
|
|
#else
|
|
{ "uart0", 2 }, /* PH0-PH1 */
|
|
#endif
|
|
{ "uart1", 2 }, /* PG6-PG7 */
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_pinctrl_desc = {
|
|
.functions = sun50i_h6_pinctrl_functions,
|
|
.num_functions = ARRAY_SIZE(sun50i_h6_pinctrl_functions),
|
|
.first_bank = SUNXI_GPIO_A,
|
|
.num_banks = 8,
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_function sun50i_h6_r_pinctrl_functions[] = {
|
|
{ "gpio_in", 0 },
|
|
{ "gpio_out", 1 },
|
|
{ "s_i2c", 3 }, /* PL0-PL1 */
|
|
{ "s_uart", 2 }, /* PL2-PL3 */
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_r_pinctrl_desc = {
|
|
.functions = sun50i_h6_r_pinctrl_functions,
|
|
.num_functions = ARRAY_SIZE(sun50i_h6_r_pinctrl_functions),
|
|
.first_bank = SUNXI_GPIO_L,
|
|
.num_banks = 2,
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_function sun50i_h616_pinctrl_functions[] = {
|
|
{ "emac0", 2 }, /* PI0-PI16 */
|
|
{ "gpio_in", 0 },
|
|
{ "gpio_out", 1 },
|
|
{ "mmc0", 2 }, /* PF0-PF5 */
|
|
{ "mmc1", 2 }, /* PG0-PG5 */
|
|
{ "mmc2", 3 }, /* PC0-PC16 */
|
|
{ "spi0", 4 }, /* PC0-PC7, PC15-PC16 */
|
|
#if IS_ENABLED(CONFIG_UART0_PORT_F)
|
|
{ "uart0", 3 }, /* PF2-PF4 */
|
|
#else
|
|
{ "uart0", 2 }, /* PH0-PH1 */
|
|
#endif
|
|
{ "uart1", 2 }, /* PG6-PG7 */
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_pinctrl_desc = {
|
|
.functions = sun50i_h616_pinctrl_functions,
|
|
.num_functions = ARRAY_SIZE(sun50i_h616_pinctrl_functions),
|
|
.first_bank = SUNXI_GPIO_A,
|
|
.num_banks = 9,
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_function sun50i_h616_r_pinctrl_functions[] = {
|
|
{ "gpio_in", 0 },
|
|
{ "gpio_out", 1 },
|
|
{ "s_i2c", 3 }, /* PL0-PL1 */
|
|
{ "s_uart", 2 }, /* PL2-PL3 */
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_r_pinctrl_desc = {
|
|
.functions = sun50i_h616_r_pinctrl_functions,
|
|
.num_functions = ARRAY_SIZE(sun50i_h616_r_pinctrl_functions),
|
|
.first_bank = SUNXI_GPIO_L,
|
|
.num_banks = 1,
|
|
};
|
|
|
|
static const struct udevice_id sunxi_pinctrl_ids[] = {
|
|
#ifdef CONFIG_PINCTRL_SUNIV_F1C100S
|
|
{
|
|
.compatible = "allwinner,suniv-f1c100s-pinctrl",
|
|
.data = (ulong)&suniv_f1c100s_pinctrl_desc,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_SUN4I_A10
|
|
{
|
|
.compatible = "allwinner,sun4i-a10-pinctrl",
|
|
.data = (ulong)&sun4i_a10_pinctrl_desc,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_SUN5I_A13
|
|
{
|
|
.compatible = "allwinner,sun5i-a10s-pinctrl",
|
|
.data = (ulong)&sun5i_a13_pinctrl_desc,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun5i-a13-pinctrl",
|
|
.data = (ulong)&sun5i_a13_pinctrl_desc,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_SUN6I_A31
|
|
{
|
|
.compatible = "allwinner,sun6i-a31-pinctrl",
|
|
.data = (ulong)&sun6i_a31_pinctrl_desc,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun6i-a31s-pinctrl",
|
|
.data = (ulong)&sun6i_a31_pinctrl_desc,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_SUN6I_A31_R
|
|
{
|
|
.compatible = "allwinner,sun6i-a31-r-pinctrl",
|
|
.data = (ulong)&sun6i_a31_r_pinctrl_desc,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_SUN7I_A20
|
|
{
|
|
.compatible = "allwinner,sun7i-a20-pinctrl",
|
|
.data = (ulong)&sun7i_a20_pinctrl_desc,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_SUN8I_A23
|
|
{
|
|
.compatible = "allwinner,sun8i-a23-pinctrl",
|
|
.data = (ulong)&sun8i_a23_pinctrl_desc,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_SUN8I_A23_R
|
|
{
|
|
.compatible = "allwinner,sun8i-a23-r-pinctrl",
|
|
.data = (ulong)&sun8i_a23_r_pinctrl_desc,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_SUN8I_A33
|
|
{
|
|
.compatible = "allwinner,sun8i-a33-pinctrl",
|
|
.data = (ulong)&sun8i_a33_pinctrl_desc,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_SUN8I_A83T
|
|
{
|
|
.compatible = "allwinner,sun8i-a83t-pinctrl",
|
|
.data = (ulong)&sun8i_a83t_pinctrl_desc,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_SUN8I_A83T_R
|
|
{
|
|
.compatible = "allwinner,sun8i-a83t-r-pinctrl",
|
|
.data = (ulong)&sun8i_a83t_r_pinctrl_desc,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_SUN8I_H3
|
|
{
|
|
.compatible = "allwinner,sun8i-h3-pinctrl",
|
|
.data = (ulong)&sun8i_h3_pinctrl_desc,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_SUN8I_H3_R
|
|
{
|
|
.compatible = "allwinner,sun8i-h3-r-pinctrl",
|
|
.data = (ulong)&sun8i_h3_r_pinctrl_desc,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_SUN7I_A20
|
|
{
|
|
.compatible = "allwinner,sun8i-r40-pinctrl",
|
|
.data = (ulong)&sun7i_a20_pinctrl_desc,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_SUN8I_V3S
|
|
{
|
|
.compatible = "allwinner,sun8i-v3-pinctrl",
|
|
.data = (ulong)&sun8i_v3s_pinctrl_desc,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun8i-v3s-pinctrl",
|
|
.data = (ulong)&sun8i_v3s_pinctrl_desc,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_SUN9I_A80
|
|
{
|
|
.compatible = "allwinner,sun9i-a80-pinctrl",
|
|
.data = (ulong)&sun9i_a80_pinctrl_desc,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_SUN9I_A80_R
|
|
{
|
|
.compatible = "allwinner,sun9i-a80-r-pinctrl",
|
|
.data = (ulong)&sun9i_a80_r_pinctrl_desc,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_SUN50I_A64
|
|
{
|
|
.compatible = "allwinner,sun50i-a64-pinctrl",
|
|
.data = (ulong)&sun50i_a64_pinctrl_desc,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_SUN50I_A64_R
|
|
{
|
|
.compatible = "allwinner,sun50i-a64-r-pinctrl",
|
|
.data = (ulong)&sun50i_a64_r_pinctrl_desc,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_SUN50I_H5
|
|
{
|
|
.compatible = "allwinner,sun50i-h5-pinctrl",
|
|
.data = (ulong)&sun50i_h5_pinctrl_desc,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_SUN50I_H6
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{
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.compatible = "allwinner,sun50i-h6-pinctrl",
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.data = (ulong)&sun50i_h6_pinctrl_desc,
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},
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#endif
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#ifdef CONFIG_PINCTRL_SUN50I_H6_R
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{
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.compatible = "allwinner,sun50i-h6-r-pinctrl",
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.data = (ulong)&sun50i_h6_r_pinctrl_desc,
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},
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#endif
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#ifdef CONFIG_PINCTRL_SUN50I_H616
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{
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.compatible = "allwinner,sun50i-h616-pinctrl",
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.data = (ulong)&sun50i_h616_pinctrl_desc,
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},
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#endif
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#ifdef CONFIG_PINCTRL_SUN50I_H616_R
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{
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.compatible = "allwinner,sun50i-h616-r-pinctrl",
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.data = (ulong)&sun50i_h616_r_pinctrl_desc,
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},
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#endif
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{}
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};
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U_BOOT_DRIVER(sunxi_pinctrl) = {
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.name = "sunxi-pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = sunxi_pinctrl_ids,
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.bind = sunxi_pinctrl_bind,
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.probe = sunxi_pinctrl_probe,
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.plat_auto = sizeof(struct sunxi_pinctrl_plat),
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.ops = &sunxi_pinctrl_ops,
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};
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