mirror of
https://github.com/AsahiLinux/u-boot
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1221ce459d
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content. (both just wrap <asm-generic/errno.h>)
Replace all include directives for <asm/errno.h> with <linux/errno.h>.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <trini@konsulko.com>
265 lines
6.8 KiB
C
265 lines
6.8 KiB
C
/*
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* LPC32xx I2C interface driver
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*
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* (C) Copyright 2014-2015 DENX Software Engineering GmbH
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* Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <i2c.h>
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#include <linux/errno.h>
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#include <asm/arch/clk.h>
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/*
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* Provide default speed and slave if target did not
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*/
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#if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED)
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#define CONFIG_SYS_I2C_LPC32XX_SPEED 350000
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#endif
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#if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE)
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#define CONFIG_SYS_I2C_LPC32XX_SLAVE 0
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#endif
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/* i2c register set */
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struct lpc32xx_i2c_registers {
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union {
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u32 rx;
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u32 tx;
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};
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u32 stat;
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u32 ctrl;
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u32 clk_hi;
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u32 clk_lo;
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u32 adr;
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u32 rxfl;
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u32 txfl;
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u32 rxb;
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u32 txb;
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u32 stx;
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u32 stxfl;
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};
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/* TX register fields */
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#define LPC32XX_I2C_TX_START 0x00000100
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#define LPC32XX_I2C_TX_STOP 0x00000200
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/* Control register values */
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#define LPC32XX_I2C_SOFT_RESET 0x00000100
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/* Status register values */
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#define LPC32XX_I2C_STAT_TFF 0x00000400
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#define LPC32XX_I2C_STAT_RFE 0x00000200
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#define LPC32XX_I2C_STAT_DRMI 0x00000008
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#define LPC32XX_I2C_STAT_NAI 0x00000004
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#define LPC32XX_I2C_STAT_TDI 0x00000001
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static struct lpc32xx_i2c_registers *lpc32xx_i2c[] = {
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(struct lpc32xx_i2c_registers *)I2C1_BASE,
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(struct lpc32xx_i2c_registers *)I2C2_BASE,
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(struct lpc32xx_i2c_registers *)(USB_BASE + 0x300)
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};
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/* Set I2C bus speed */
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static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap,
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unsigned int speed)
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{
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int half_period;
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if (speed == 0)
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return -EINVAL;
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/* OTG I2C clock source and CLK registers are different */
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if (adap->hwadapnr == 2) {
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half_period = (get_periph_clk_rate() / speed) / 2;
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if (half_period > 0xFF)
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return -EINVAL;
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} else {
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half_period = (get_hclk_clk_rate() / speed) / 2;
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if (half_period > 0x3FF)
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return -EINVAL;
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}
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writel(half_period, &lpc32xx_i2c[adap->hwadapnr]->clk_hi);
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writel(half_period, &lpc32xx_i2c[adap->hwadapnr]->clk_lo);
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return 0;
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}
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/* I2C init called by cmd_i2c when doing 'i2c reset'. */
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static void _i2c_init(struct i2c_adapter *adap,
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int requested_speed, int slaveadd)
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{
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struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
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/* soft reset (auto-clears) */
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writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl);
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/* set HI and LO periods for half of the default speed */
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lpc32xx_i2c_set_bus_speed(adap, requested_speed);
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}
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/* I2C probe called by cmd_i2c when doing 'i2c probe'. */
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static int lpc32xx_i2c_probe(struct i2c_adapter *adap, u8 dev)
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{
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struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
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int stat;
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/* Soft-reset the controller */
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writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl);
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while (readl(&i2c->ctrl) & LPC32XX_I2C_SOFT_RESET)
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;
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/* Addre slave for write with start before and stop after */
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writel((dev<<1) | LPC32XX_I2C_TX_START | LPC32XX_I2C_TX_STOP,
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&i2c->tx);
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/* wait for end of transation */
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while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI))
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;
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/* was there no acknowledge? */
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return (stat & LPC32XX_I2C_STAT_NAI) ? -1 : 0;
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}
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/*
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* I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
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* Begin write, send address byte(s), begin read, receive data bytes, end.
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*/
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static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
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int alen, u8 *data, int length)
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{
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struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
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int stat, wlen;
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/* Soft-reset the controller */
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writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl);
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while (readl(&i2c->ctrl) & LPC32XX_I2C_SOFT_RESET)
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;
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/* do we need to write an address at all? */
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if (alen) {
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/* Address slave in write mode */
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writel((dev<<1) | LPC32XX_I2C_TX_START, &i2c->tx);
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/* write address bytes */
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while (alen--) {
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/* compute address byte + stop for the last one */
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int a = (addr >> (8 * alen)) & 0xff;
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if (!alen)
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a |= LPC32XX_I2C_TX_STOP;
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/* Send address byte */
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writel(a, &i2c->tx);
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}
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/* wait for end of transation */
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while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI))
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;
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/* clear end-of-transaction flag */
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writel(1, &i2c->stat);
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}
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/* do we have to read data at all? */
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if (length) {
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/* Address slave in read mode */
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writel(1 | (dev<<1) | LPC32XX_I2C_TX_START, &i2c->tx);
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wlen = length;
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/* get data */
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while (length | wlen) {
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/* read status for TFF and RFE */
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stat = readl(&i2c->stat);
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/* must we, can we write a trigger byte? */
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if ((wlen > 0)
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& (!(stat & LPC32XX_I2C_STAT_TFF))) {
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wlen--;
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/* write trigger byte + stop if last */
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writel(wlen ? 0 :
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LPC32XX_I2C_TX_STOP, &i2c->tx);
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}
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/* must we, can we read a data byte? */
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if ((length > 0)
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& (!(stat & LPC32XX_I2C_STAT_RFE))) {
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length--;
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/* read byte */
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*(data++) = readl(&i2c->rx);
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}
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}
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/* wait for end of transation */
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while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI))
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;
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/* clear end-of-transaction flag */
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writel(1, &i2c->stat);
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}
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/* success */
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return 0;
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}
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/*
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* I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
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* Begin write, send address byte(s), send data bytes, end.
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*/
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static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
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int alen, u8 *data, int length)
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{
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struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
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int stat;
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/* Soft-reset the controller */
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writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl);
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while (readl(&i2c->ctrl) & LPC32XX_I2C_SOFT_RESET)
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;
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/* do we need to write anything at all? */
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if (alen | length)
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/* Address slave in write mode */
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writel((dev<<1) | LPC32XX_I2C_TX_START, &i2c->tx);
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else
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return 0;
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/* write address bytes */
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while (alen) {
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/* wait for transmit fifo not full */
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stat = readl(&i2c->stat);
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if (!(stat & LPC32XX_I2C_STAT_TFF)) {
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alen--;
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int a = (addr >> (8 * alen)) & 0xff;
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if (!(alen | length))
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a |= LPC32XX_I2C_TX_STOP;
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/* Send address byte */
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writel(a, &i2c->tx);
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}
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}
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while (length) {
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/* wait for transmit fifo not full */
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stat = readl(&i2c->stat);
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if (!(stat & LPC32XX_I2C_STAT_TFF)) {
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/* compute data byte, add stop if length==0 */
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length--;
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int d = *(data++);
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if (!length)
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d |= LPC32XX_I2C_TX_STOP;
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/* Send data byte */
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writel(d, &i2c->tx);
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}
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}
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/* wait for end of transation */
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while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI))
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;
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/* clear end-of-transaction flag */
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writel(1, &i2c->stat);
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return 0;
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}
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U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, _i2c_init, lpc32xx_i2c_probe,
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lpc32xx_i2c_read, lpc32xx_i2c_write,
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lpc32xx_i2c_set_bus_speed,
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CONFIG_SYS_I2C_LPC32XX_SPEED,
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CONFIG_SYS_I2C_LPC32XX_SLAVE,
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0)
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U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, _i2c_init, lpc32xx_i2c_probe,
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lpc32xx_i2c_read, lpc32xx_i2c_write,
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lpc32xx_i2c_set_bus_speed,
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CONFIG_SYS_I2C_LPC32XX_SPEED,
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CONFIG_SYS_I2C_LPC32XX_SLAVE,
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1)
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U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, _i2c_init, NULL,
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lpc32xx_i2c_read, lpc32xx_i2c_write,
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lpc32xx_i2c_set_bus_speed,
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100000,
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0,
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2)
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