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https://github.com/AsahiLinux/u-boot
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6e7df1d151
At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
253 lines
5.5 KiB
C
253 lines
5.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2018
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* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <irq_func.h>
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#include <log.h>
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#include <status_led.h>
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#include <sysinfo.h>
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#include <time.h>
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#include <timer.h>
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#include <watchdog.h>
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#include <asm/global_data.h>
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#include <asm/ptrace.h>
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#include <linux/bitops.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CFG_SYS_WATCHDOG_FREQ
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#define CFG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
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#endif
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/**
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* struct mpc83xx_timer_priv - Private data structure for MPC83xx timer driver
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* @decrementer_count: Value to which the decrementer register should be re-set
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* to when a timer interrupt occurs, thus determines the
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* interrupt frequency (value for 1e6/HZ microseconds)
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* @timestamp: Counter for the number of timer interrupts that have
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* occurred (i.e. can be used to trigger events
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* periodically in the timer interrupt)
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*/
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struct mpc83xx_timer_priv {
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uint decrementer_count;
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ulong timestamp;
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};
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/*
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* Bitmask for enabling the time base in the SPCR (System Priority
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* Configuration Register)
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*/
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static const u32 SPCR_TBEN_MASK = BIT(31 - 9);
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/**
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* get_dec() - Get the value of the decrementer register
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*
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* Return: The value of the decrementer register
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*/
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static inline unsigned long get_dec(void)
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{
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unsigned long val;
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asm volatile ("mfdec %0" : "=r" (val) : );
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return val;
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}
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/**
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* set_dec() - Set the value of the decrementer register
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* @val: The value of the decrementer register to be set
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*/
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static inline void set_dec(unsigned long val)
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{
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if (val)
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asm volatile ("mtdec %0"::"r" (val));
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}
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/**
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* mftbu() - Get value of TBU (upper time base) register
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*
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* Return: Value of the TBU register
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*/
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static inline u32 mftbu(void)
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{
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u32 rval;
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asm volatile("mftbu %0" : "=r" (rval));
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return rval;
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}
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/**
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* mftb() - Get value of TBL (lower time base) register
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*
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* Return: Value of the TBL register
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*/
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static inline u32 mftb(void)
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{
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u32 rval;
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asm volatile("mftb %0" : "=r" (rval));
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return rval;
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}
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/*
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* TODO(mario.six@gdsys.cc): This should really be done by timer_init, and the
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* interrupt init should go into a interrupt driver.
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*/
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int interrupt_init(void)
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{
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immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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struct udevice *csb;
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struct udevice *sysinfo;
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struct udevice *timer;
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struct mpc83xx_timer_priv *timer_priv;
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struct clk clock;
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int ret;
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ret = uclass_first_device_err(UCLASS_TIMER, &timer);
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if (ret) {
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debug("%s: Could not find timer device (error: %d)",
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__func__, ret);
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return ret;
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}
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timer_priv = dev_get_priv(timer);
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if (sysinfo_get(&sysinfo)) {
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debug("%s: sysinfo device could not be fetched.\n", __func__);
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return -ENOENT;
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}
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ret = uclass_get_device_by_phandle(UCLASS_SIMPLE_BUS, sysinfo,
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"csb", &csb);
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if (ret) {
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debug("%s: Could not retrieve CSB device (error: %d)",
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__func__, ret);
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return ret;
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}
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ret = clk_get_by_index(csb, 0, &clock);
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if (ret) {
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debug("%s: Could not retrieve clock (error: %d)",
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__func__, ret);
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return ret;
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}
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timer_priv->decrementer_count = (clk_get_rate(&clock) / 4)
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/ CONFIG_SYS_HZ;
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/* Enable e300 time base */
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setbits_be32(&immr->sysconf.spcr, SPCR_TBEN_MASK);
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set_dec(timer_priv->decrementer_count);
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/* Switch on interrupts */
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set_msr(get_msr() | MSR_EE);
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return 0;
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}
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/**
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* timer_interrupt() - Handler for the timer interrupt
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* @regs: Array of register values
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*/
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void timer_interrupt(struct pt_regs *regs)
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{
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struct udevice *timer = gd->timer;
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struct mpc83xx_timer_priv *priv;
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/*
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* During initialization, gd->timer might not be set yet, but the timer
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* interrupt may already be enabled. In this case, wait for the
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* initialization to complete
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*/
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if (!timer)
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return;
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priv = dev_get_priv(timer);
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/* Restore Decrementer Count */
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set_dec(priv->decrementer_count);
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priv->timestamp++;
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#if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
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if (CFG_SYS_WATCHDOG_FREQ && (priv->timestamp % (CFG_SYS_WATCHDOG_FREQ)) == 0)
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schedule();
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#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
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#ifdef CONFIG_LED_STATUS
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status_led_tick(priv->timestamp);
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#endif /* CONFIG_LED_STATUS */
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}
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void wait_ticks(ulong ticks)
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{
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ulong end = get_ticks() + ticks;
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while (end > get_ticks())
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schedule();
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}
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static u64 mpc83xx_timer_get_count(struct udevice *dev)
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{
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u32 tbu, tbl;
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/*
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* To make sure that no tbl overflow occurred between reading tbl and
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* tbu, read tbu again, and compare it with the previously read tbu
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* value: If they're different, a tbl overflow has occurred.
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*/
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do {
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tbu = mftbu();
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tbl = mftb();
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} while (tbu != mftbu());
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return (tbu * 0x10000ULL) + tbl;
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}
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static int mpc83xx_timer_probe(struct udevice *dev)
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{
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struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct clk clock;
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int ret;
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ret = interrupt_init();
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if (ret) {
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debug("%s: interrupt_init failed (err = %d)\n",
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dev->name, ret);
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return ret;
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}
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ret = clk_get_by_index(dev, 0, &clock);
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if (ret) {
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debug("%s: Could not retrieve clock (err = %d)\n",
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dev->name, ret);
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return ret;
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}
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uc_priv->clock_rate = (clk_get_rate(&clock) + 3L) / 4L;
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return 0;
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}
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static const struct timer_ops mpc83xx_timer_ops = {
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.get_count = mpc83xx_timer_get_count,
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};
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static const struct udevice_id mpc83xx_timer_ids[] = {
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{ .compatible = "fsl,mpc83xx-timer" },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(mpc83xx_timer) = {
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.name = "mpc83xx_timer",
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.id = UCLASS_TIMER,
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.of_match = mpc83xx_timer_ids,
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.probe = mpc83xx_timer_probe,
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.ops = &mpc83xx_timer_ops,
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.priv_auto = sizeof(struct mpc83xx_timer_priv),
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};
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