mirror of
https://github.com/AsahiLinux/u-boot
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6e7df1d151
At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
828 lines
20 KiB
C
828 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
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*
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* Dave Liu <daveliu@freescale.com>
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* based on source code of Shlomi Gridish
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*/
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#include <common.h>
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#include <malloc.h>
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#include <command.h>
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#include <asm/global_data.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <linux/immap_qe.h>
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#include <fsl_qe.h>
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#include <mmc.h>
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#include <u-boot/crc.h>
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#ifdef CONFIG_ARCH_LS1021A
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#include <asm/arch/immap_ls102xa.h>
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#endif
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#ifdef CONFIG_ARM64
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#include <asm/armv8/mmu.h>
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#include <asm/arch/cpu.h>
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#endif
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#define MPC85xx_DEVDISR_QE_DISABLE 0x1
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qe_map_t *qe_immr;
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#ifdef CONFIG_QE
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static qe_snum_t snums[QE_NUM_OF_SNUM];
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data)
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{
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u32 cecr;
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if (cmd == QE_RESET) {
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out_be32(&qe_immr->cp.cecr, (u32)(cmd | QE_CR_FLG));
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} else {
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out_be32(&qe_immr->cp.cecdr, cmd_data);
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out_be32(&qe_immr->cp.cecr, (sbc | QE_CR_FLG |
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((u32)mcn << QE_CR_PROTOCOL_SHIFT) | cmd));
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}
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/* Wait for the QE_CR_FLG to clear */
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do {
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cecr = in_be32(&qe_immr->cp.cecr);
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} while (cecr & QE_CR_FLG);
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}
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#ifdef CONFIG_QE
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uint qe_muram_alloc(uint size, uint align)
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{
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uint retloc;
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uint align_mask, off;
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uint savebase;
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align_mask = align - 1;
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savebase = gd->arch.mp_alloc_base;
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off = gd->arch.mp_alloc_base & align_mask;
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if (off != 0)
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gd->arch.mp_alloc_base += (align - off);
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off = size & align_mask;
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if (off != 0)
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size += (align - off);
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if ((gd->arch.mp_alloc_base + size) >= gd->arch.mp_alloc_top) {
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gd->arch.mp_alloc_base = savebase;
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printf("%s: ran out of ram.\n", __func__);
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}
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retloc = gd->arch.mp_alloc_base;
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gd->arch.mp_alloc_base += size;
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memset((void *)&qe_immr->muram[retloc], 0, size);
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__asm__ __volatile__("sync");
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return retloc;
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}
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#endif
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void *qe_muram_addr(uint offset)
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{
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return (void *)&qe_immr->muram[offset];
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}
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#ifdef CONFIG_QE
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static void qe_sdma_init(void)
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{
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sdma_t *p;
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uint sdma_buffer_base;
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p = (sdma_t *)&qe_immr->sdma;
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/* All of DMA transaction in bus 1 */
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out_be32(&p->sdaqr, 0);
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out_be32(&p->sdaqmr, 0);
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/* Allocate 2KB temporary buffer for sdma */
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sdma_buffer_base = qe_muram_alloc(2048, 4096);
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out_be32(&p->sdwbcr, sdma_buffer_base & QE_SDEBCR_BA_MASK);
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/* Clear sdma status */
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out_be32(&p->sdsr, 0x03000000);
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/* Enable global mode on bus 1, and 2KB buffer size */
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out_be32(&p->sdmr, QE_SDMR_GLB_1_MSK | (0x3 << QE_SDMR_CEN_SHIFT));
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}
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/* This table is a list of the serial numbers of the Threads, taken from the
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* "SNUM Table" chart in the QE Reference Manual. The order is not important,
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* we just need to know what the SNUMs are for the threads.
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*/
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static u8 thread_snum[] = {
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/* Evthreads 16-29 are not supported in MPC8309 */
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0x04, 0x05, 0x0c, 0x0d,
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0x14, 0x15, 0x1c, 0x1d,
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0x24, 0x25, 0x2c, 0x2d,
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0x34, 0x35,
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0x88, 0x89, 0x98, 0x99,
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0xa8, 0xa9, 0xb8, 0xb9,
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0xc8, 0xc9, 0xd8, 0xd9,
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0xe8, 0xe9, 0x08, 0x09,
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0x18, 0x19, 0x28, 0x29,
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0x38, 0x39, 0x48, 0x49,
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0x58, 0x59, 0x68, 0x69,
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0x78, 0x79, 0x80, 0x81
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};
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static void qe_snums_init(void)
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{
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int i;
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for (i = 0; i < QE_NUM_OF_SNUM; i++) {
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snums[i].state = QE_SNUM_STATE_FREE;
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snums[i].num = thread_snum[i];
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}
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}
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int qe_get_snum(void)
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{
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int snum = -EBUSY;
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int i;
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for (i = 0; i < QE_NUM_OF_SNUM; i++) {
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if (snums[i].state == QE_SNUM_STATE_FREE) {
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snums[i].state = QE_SNUM_STATE_USED;
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snum = snums[i].num;
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break;
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}
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}
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return snum;
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}
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void qe_put_snum(u8 snum)
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{
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int i;
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for (i = 0; i < QE_NUM_OF_SNUM; i++) {
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if (snums[i].num == snum) {
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snums[i].state = QE_SNUM_STATE_FREE;
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break;
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}
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}
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}
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#ifdef CONFIG_TFABOOT
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void qe_init(uint qe_base)
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{
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enum boot_src src = get_boot_src();
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/* Init the QE IMMR base */
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qe_immr = (qe_map_t *)qe_base;
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if (src == BOOT_SOURCE_IFC_NOR) {
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/*
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* Upload microcode to IRAM for those SOCs
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* which do not have ROM in QE.
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*/
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qe_upload_firmware((const void *)(CONFIG_SYS_QE_FW_ADDR +
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CFG_SYS_FSL_IFC_BASE));
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/* enable the microcode in IRAM */
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out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
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}
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gd->arch.mp_alloc_base = QE_DATAONLY_BASE;
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gd->arch.mp_alloc_top = gd->arch.mp_alloc_base + QE_DATAONLY_SIZE;
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qe_sdma_init();
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qe_snums_init();
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}
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#else
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void qe_init(uint qe_base)
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{
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/* Init the QE IMMR base */
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qe_immr = (qe_map_t *)qe_base;
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#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NOR
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/*
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* Upload microcode to IRAM for those SOCs which do not have ROM in QE.
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*/
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qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR);
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/* enable the microcode in IRAM */
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out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
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#endif
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gd->arch.mp_alloc_base = QE_DATAONLY_BASE;
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gd->arch.mp_alloc_top = gd->arch.mp_alloc_base + QE_DATAONLY_SIZE;
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qe_sdma_init();
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qe_snums_init();
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}
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#endif
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#endif
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#ifdef CONFIG_U_QE
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#ifdef CONFIG_TFABOOT
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void u_qe_init(void)
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{
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enum boot_src src = get_boot_src();
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qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
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void *addr = (void *)CONFIG_SYS_QE_FW_ADDR;
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if (src == BOOT_SOURCE_IFC_NOR)
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addr = (void *)(CONFIG_SYS_QE_FW_ADDR +
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CFG_SYS_FSL_IFC_BASE);
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if (src == BOOT_SOURCE_QSPI_NOR)
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addr = (void *)(CONFIG_SYS_QE_FW_ADDR +
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CFG_SYS_FSL_QSPI_BASE);
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if (src == BOOT_SOURCE_SD_MMC) {
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int dev = CONFIG_SYS_MMC_ENV_DEV;
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u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
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u32 blk = CONFIG_SYS_QE_FW_ADDR / 512;
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if (mmc_initialize(gd->bd)) {
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printf("%s: mmc_initialize() failed\n", __func__);
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return;
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}
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addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
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struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
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if (!mmc) {
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free(addr);
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printf("\nMMC cannot find device for ucode\n");
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} else {
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printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
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dev, blk, cnt);
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mmc_init(mmc);
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(void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
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addr);
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}
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}
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if (!u_qe_upload_firmware(addr))
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out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
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if (src == BOOT_SOURCE_SD_MMC)
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free(addr);
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}
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#else
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void u_qe_init(void)
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{
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qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
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void *addr = (void *)CONFIG_SYS_QE_FW_ADDR;
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#ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
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int dev = CONFIG_SYS_MMC_ENV_DEV;
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u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
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u32 blk = CONFIG_SYS_QE_FW_ADDR / 512;
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if (mmc_initialize(gd->bd)) {
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printf("%s: mmc_initialize() failed\n", __func__);
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return;
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}
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addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
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struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
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if (!mmc) {
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printf("\nMMC cannot find device for ucode\n");
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} else {
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printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
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dev, blk, cnt);
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mmc_init(mmc);
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(void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
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addr);
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}
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#endif
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if (!u_qe_upload_firmware(addr))
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out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
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#ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
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free(addr);
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#endif
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}
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#endif
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#endif
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#ifdef CONFIG_U_QE
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void u_qe_resume(void)
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{
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qe_map_t *qe_immrr;
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qe_immrr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
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u_qe_firmware_resume((const void *)CONFIG_SYS_QE_FW_ADDR, qe_immrr);
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out_be32(&qe_immrr->iram.iready, QE_IRAM_READY);
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}
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#endif
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void qe_reset(void)
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{
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qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
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(u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
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}
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#ifdef CONFIG_QE
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void qe_assign_page(uint snum, uint para_ram_base)
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{
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u32 cecr;
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out_be32(&qe_immr->cp.cecdr, para_ram_base);
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out_be32(&qe_immr->cp.cecr, ((u32)snum << QE_CR_ASSIGN_PAGE_SNUM_SHIFT)
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| QE_CR_FLG | QE_ASSIGN_PAGE);
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/* Wait for the QE_CR_FLG to clear */
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do {
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cecr = in_be32(&qe_immr->cp.cecr);
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} while (cecr & QE_CR_FLG);
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}
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#endif
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/*
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* brg: 0~15 as BRG1~BRG16
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* rate: baud rate
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* BRG input clock comes from the BRGCLK (internal clock generated from
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* the QE clock, it is one-half of the QE clock), If need the clock source
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* from CLKn pin, we have te change the function.
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*/
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#define BRG_CLK (gd->arch.brg_clk)
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#ifdef CONFIG_QE
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int qe_set_brg(uint brg, uint rate)
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{
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uint *bp;
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u32 divisor;
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u32 val;
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int div16 = 0;
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if (brg >= QE_NUM_OF_BRGS)
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return -EINVAL;
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bp = (uint *)&qe_immr->brg.brgc1;
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bp += brg;
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divisor = (BRG_CLK / rate);
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if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
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div16 = 1;
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divisor /= 16;
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}
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/* CHECK TODO */
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/*
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* was
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* *bp = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
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* __asm__ __volatile__("sync");
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*/
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val = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
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if (div16)
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val |= QE_BRGC_DIV16;
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out_be32(bp, val);
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return 0;
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}
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#endif
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/* Set ethernet MII clock master */
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int qe_set_mii_clk_src(int ucc_num)
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{
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u32 cmxgcr;
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/* check if the UCC number is in range. */
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if ((ucc_num > UCC_MAX_NUM - 1) || ucc_num < 0) {
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printf("%s: ucc num not in ranges\n", __func__);
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return -EINVAL;
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}
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cmxgcr = in_be32(&qe_immr->qmx.cmxgcr);
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cmxgcr &= ~QE_CMXGCR_MII_ENET_MNG_MASK;
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cmxgcr |= (ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
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out_be32(&qe_immr->qmx.cmxgcr, cmxgcr);
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return 0;
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}
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/* Firmware information stored here for qe_get_firmware_info() */
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static struct qe_firmware_info qe_firmware_info;
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/*
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* Set to 1 if QE firmware has been uploaded, and therefore
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* qe_firmware_info contains valid data.
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*/
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static int qe_firmware_uploaded;
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/*
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* Upload a QE microcode
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*
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* This function is a worker function for qe_upload_firmware(). It does
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* the actual uploading of the microcode.
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*/
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static void qe_upload_microcode(const void *base,
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const struct qe_microcode *ucode)
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{
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const u32 *code = base + be32_to_cpu(ucode->code_offset);
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unsigned int i;
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if (ucode->major || ucode->minor || ucode->revision)
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printf("QE: uploading microcode '%s' version %u.%u.%u\n",
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(char *)ucode->id, (u16)ucode->major, (u16)ucode->minor,
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(u16)ucode->revision);
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else
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printf("QE: uploading microcode '%s'\n", (char *)ucode->id);
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/* Use auto-increment */
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out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
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QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
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for (i = 0; i < be32_to_cpu(ucode->count); i++)
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out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
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}
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/*
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* Upload a microcode to the I-RAM at a specific address.
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*
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* See Documentation/powerpc/qe_firmware.rst in the Linux kernel tree for
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* information on QE microcode uploading.
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*
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* Currently, only version 1 is supported, so the 'version' field must be
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* set to 1.
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*
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* The SOC model and revision are not validated, they are only displayed for
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* informational purposes.
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*
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* 'calc_size' is the calculated size, in bytes, of the firmware structure and
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* all of the microcode structures, minus the CRC.
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*
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* 'length' is the size that the structure says it is, including the CRC.
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*/
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int qe_upload_firmware(const struct qe_firmware *firmware)
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{
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unsigned int i;
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unsigned int j;
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u32 crc;
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size_t calc_size = sizeof(struct qe_firmware);
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size_t length;
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const struct qe_header *hdr;
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#ifdef CONFIG_DEEP_SLEEP
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#ifdef CONFIG_ARCH_LS1021A
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struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
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#else
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ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
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#endif
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#endif
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if (!firmware) {
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printf("Invalid address\n");
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return -EINVAL;
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}
|
|
|
|
hdr = &firmware->header;
|
|
length = be32_to_cpu(hdr->length);
|
|
|
|
/* Check the magic */
|
|
if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
|
|
(hdr->magic[2] != 'F')) {
|
|
printf("QE microcode not found\n");
|
|
#ifdef CONFIG_DEEP_SLEEP
|
|
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
|
|
#endif
|
|
return -EPERM;
|
|
}
|
|
|
|
/* Check the version */
|
|
if (hdr->version != 1) {
|
|
printf("Unsupported version\n");
|
|
return -EPERM;
|
|
}
|
|
|
|
/* Validate some of the fields */
|
|
if (firmware->count < 1 || firmware->count > MAX_QE_RISC) {
|
|
printf("Invalid data\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Validate the length and check if there's a CRC */
|
|
calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
|
|
|
|
for (i = 0; i < firmware->count; i++)
|
|
/*
|
|
* For situations where the second RISC uses the same microcode
|
|
* as the first, the 'code_offset' and 'count' fields will be
|
|
* zero, so it's okay to add those.
|
|
*/
|
|
calc_size += sizeof(u32) *
|
|
be32_to_cpu(firmware->microcode[i].count);
|
|
|
|
/* Validate the length */
|
|
if (length != calc_size + sizeof(u32)) {
|
|
printf("Invalid length\n");
|
|
return -EPERM;
|
|
}
|
|
|
|
/*
|
|
* Validate the CRC. We would normally call crc32_no_comp(), but that
|
|
* function isn't available unless you turn on JFFS support.
|
|
*/
|
|
crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
|
|
if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
|
|
printf("Firmware CRC is invalid\n");
|
|
return -EIO;
|
|
}
|
|
|
|
/*
|
|
* If the microcode calls for it, split the I-RAM.
|
|
*/
|
|
if (!firmware->split) {
|
|
out_be16(&qe_immr->cp.cercr,
|
|
in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
|
|
}
|
|
|
|
if (firmware->soc.model)
|
|
printf("Firmware '%s' for %u V%u.%u\n",
|
|
firmware->id, be16_to_cpu(firmware->soc.model),
|
|
firmware->soc.major, firmware->soc.minor);
|
|
else
|
|
printf("Firmware '%s'\n", firmware->id);
|
|
|
|
/*
|
|
* The QE only supports one microcode per RISC, so clear out all the
|
|
* saved microcode information and put in the new.
|
|
*/
|
|
memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
|
|
strncpy(qe_firmware_info.id, (char *)firmware->id, 62);
|
|
qe_firmware_info.extended_modes = firmware->extended_modes;
|
|
memcpy(qe_firmware_info.vtraps, firmware->vtraps,
|
|
sizeof(firmware->vtraps));
|
|
qe_firmware_uploaded = 1;
|
|
|
|
/* Loop through each microcode. */
|
|
for (i = 0; i < firmware->count; i++) {
|
|
const struct qe_microcode *ucode = &firmware->microcode[i];
|
|
|
|
/* Upload a microcode if it's present */
|
|
if (ucode->code_offset)
|
|
qe_upload_microcode(firmware, ucode);
|
|
|
|
/* Program the traps for this processor */
|
|
for (j = 0; j < 16; j++) {
|
|
u32 trap = be32_to_cpu(ucode->traps[j]);
|
|
|
|
if (trap)
|
|
out_be32(&qe_immr->rsp[i].tibcr[j], trap);
|
|
}
|
|
|
|
/* Enable traps */
|
|
out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_U_QE
|
|
/*
|
|
* Upload a microcode to the I-RAM at a specific address.
|
|
*
|
|
* See Documentation/powerpc/qe_firmware.rst in the Linux kernel tree for
|
|
* information on QE microcode uploading.
|
|
*
|
|
* Currently, only version 1 is supported, so the 'version' field must be
|
|
* set to 1.
|
|
*
|
|
* The SOC model and revision are not validated, they are only displayed for
|
|
* informational purposes.
|
|
*
|
|
* 'calc_size' is the calculated size, in bytes, of the firmware structure and
|
|
* all of the microcode structures, minus the CRC.
|
|
*
|
|
* 'length' is the size that the structure says it is, including the CRC.
|
|
*/
|
|
int u_qe_upload_firmware(const struct qe_firmware *firmware)
|
|
{
|
|
unsigned int i;
|
|
unsigned int j;
|
|
u32 crc;
|
|
size_t calc_size = sizeof(struct qe_firmware);
|
|
size_t length;
|
|
const struct qe_header *hdr;
|
|
#ifdef CONFIG_DEEP_SLEEP
|
|
#ifdef CONFIG_ARCH_LS1021A
|
|
struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
|
|
#else
|
|
ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
|
#endif
|
|
#endif
|
|
if (!firmware) {
|
|
printf("Invalid address\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
hdr = &firmware->header;
|
|
length = be32_to_cpu(hdr->length);
|
|
|
|
/* Check the magic */
|
|
if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
|
|
(hdr->magic[2] != 'F')) {
|
|
printf("Not a microcode\n");
|
|
#ifdef CONFIG_DEEP_SLEEP
|
|
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
|
|
#endif
|
|
return -EPERM;
|
|
}
|
|
|
|
/* Check the version */
|
|
if (hdr->version != 1) {
|
|
printf("Unsupported version\n");
|
|
return -EPERM;
|
|
}
|
|
|
|
/* Validate some of the fields */
|
|
if (firmware->count < 1 || firmware->count > MAX_QE_RISC) {
|
|
printf("Invalid data\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Validate the length and check if there's a CRC */
|
|
calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
|
|
|
|
for (i = 0; i < firmware->count; i++)
|
|
/*
|
|
* For situations where the second RISC uses the same microcode
|
|
* as the first, the 'code_offset' and 'count' fields will be
|
|
* zero, so it's okay to add those.
|
|
*/
|
|
calc_size += sizeof(u32) *
|
|
be32_to_cpu(firmware->microcode[i].count);
|
|
|
|
/* Validate the length */
|
|
if (length != calc_size + sizeof(u32)) {
|
|
printf("Invalid length\n");
|
|
return -EPERM;
|
|
}
|
|
|
|
/*
|
|
* Validate the CRC. We would normally call crc32_no_comp(), but that
|
|
* function isn't available unless you turn on JFFS support.
|
|
*/
|
|
crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
|
|
if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
|
|
printf("Firmware CRC is invalid\n");
|
|
return -EIO;
|
|
}
|
|
|
|
/*
|
|
* If the microcode calls for it, split the I-RAM.
|
|
*/
|
|
if (!firmware->split) {
|
|
out_be16(&qe_immr->cp.cercr,
|
|
in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
|
|
}
|
|
|
|
if (firmware->soc.model)
|
|
printf("Firmware '%s' for %u V%u.%u\n",
|
|
firmware->id, be16_to_cpu(firmware->soc.model),
|
|
firmware->soc.major, firmware->soc.minor);
|
|
else
|
|
printf("Firmware '%s'\n", firmware->id);
|
|
|
|
/* Loop through each microcode. */
|
|
for (i = 0; i < firmware->count; i++) {
|
|
const struct qe_microcode *ucode = &firmware->microcode[i];
|
|
|
|
/* Upload a microcode if it's present */
|
|
if (ucode->code_offset)
|
|
qe_upload_microcode(firmware, ucode);
|
|
|
|
/* Program the traps for this processor */
|
|
for (j = 0; j < 16; j++) {
|
|
u32 trap = be32_to_cpu(ucode->traps[j]);
|
|
|
|
if (trap)
|
|
out_be32(&qe_immr->rsp[i].tibcr[j], trap);
|
|
}
|
|
|
|
/* Enable traps */
|
|
out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_U_QE
|
|
int u_qe_firmware_resume(const struct qe_firmware *firmware, qe_map_t *qe_immrr)
|
|
{
|
|
unsigned int i;
|
|
unsigned int j;
|
|
const struct qe_header *hdr;
|
|
const u32 *code;
|
|
#ifdef CONFIG_DEEP_SLEEP
|
|
#ifdef CONFIG_PPC
|
|
ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
|
#else
|
|
struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
|
|
#endif
|
|
#endif
|
|
|
|
if (!firmware)
|
|
return -EINVAL;
|
|
|
|
hdr = &firmware->header;
|
|
|
|
/* Check the magic */
|
|
if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
|
|
(hdr->magic[2] != 'F')) {
|
|
#ifdef CONFIG_DEEP_SLEEP
|
|
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
|
|
#endif
|
|
return -EPERM;
|
|
}
|
|
|
|
/*
|
|
* If the microcode calls for it, split the I-RAM.
|
|
*/
|
|
if (!firmware->split) {
|
|
out_be16(&qe_immrr->cp.cercr,
|
|
in_be16(&qe_immrr->cp.cercr) | QE_CP_CERCR_CIR);
|
|
}
|
|
|
|
/* Loop through each microcode. */
|
|
for (i = 0; i < firmware->count; i++) {
|
|
const struct qe_microcode *ucode = &firmware->microcode[i];
|
|
|
|
/* Upload a microcode if it's present */
|
|
if (!ucode->code_offset)
|
|
return 0;
|
|
|
|
code = (const void *)firmware + be32_to_cpu(ucode->code_offset);
|
|
|
|
/* Use auto-increment */
|
|
out_be32(&qe_immrr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
|
|
QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
|
|
|
|
for (i = 0; i < be32_to_cpu(ucode->count); i++)
|
|
out_be32(&qe_immrr->iram.idata, be32_to_cpu(code[i]));
|
|
|
|
/* Program the traps for this processor */
|
|
for (j = 0; j < 16; j++) {
|
|
u32 trap = be32_to_cpu(ucode->traps[j]);
|
|
|
|
if (trap)
|
|
out_be32(&qe_immrr->rsp[i].tibcr[j], trap);
|
|
}
|
|
|
|
/* Enable traps */
|
|
out_be32(&qe_immrr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
struct qe_firmware_info *qe_get_firmware_info(void)
|
|
{
|
|
return qe_firmware_uploaded ? &qe_firmware_info : NULL;
|
|
}
|
|
|
|
static int qe_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
|
|
{
|
|
ulong addr;
|
|
|
|
if (argc < 3)
|
|
return cmd_usage(cmdtp);
|
|
|
|
if (strcmp(argv[1], "fw") == 0) {
|
|
addr = hextoul(argv[2], NULL);
|
|
|
|
if (!addr) {
|
|
printf("Invalid address\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* If a length was supplied, compare that with the 'length'
|
|
* field.
|
|
*/
|
|
|
|
if (argc > 3) {
|
|
ulong length = hextoul(argv[3], NULL);
|
|
struct qe_firmware *firmware = (void *)addr;
|
|
|
|
if (length != be32_to_cpu(firmware->header.length)) {
|
|
printf("Length mismatch\n");
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
return qe_upload_firmware((const struct qe_firmware *)addr);
|
|
}
|
|
|
|
return cmd_usage(cmdtp);
|
|
}
|
|
|
|
U_BOOT_CMD(
|
|
qe, 4, 0, qe_cmd,
|
|
"QUICC Engine commands",
|
|
"fw <addr> [<length>] - Upload firmware binary at address <addr> to the QE,\n"
|
|
"\twith optional length <length> verification."
|
|
);
|