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https://github.com/AsahiLinux/u-boot
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84404d8165
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so fix some debug strings with fdt_addr_t to be able to handle both sizes. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
695 lines
16 KiB
C
695 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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#define LOG_CATEGORY UCLASS_PHY
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#include <common.h>
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#include <clk.h>
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#include <clk-uclass.h>
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#include <div64.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <generic-phy.h>
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#include <log.h>
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#include <reset.h>
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#include <syscon.h>
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#include <usb.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <dm/lists.h>
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#include <dm/of_access.h>
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <power/regulator.h>
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/* USBPHYC registers */
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#define STM32_USBPHYC_PLL 0x0
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#define STM32_USBPHYC_MISC 0x8
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#define STM32_USBPHYC_TUNE(X) (0x10C + ((X) * 0x100))
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/* STM32_USBPHYC_PLL bit fields */
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#define PLLNDIV GENMASK(6, 0)
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#define PLLNDIV_SHIFT 0
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#define PLLFRACIN GENMASK(25, 10)
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#define PLLFRACIN_SHIFT 10
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#define PLLEN BIT(26)
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#define PLLSTRB BIT(27)
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#define PLLSTRBYP BIT(28)
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#define PLLFRACCTL BIT(29)
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#define PLLDITHEN0 BIT(30)
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#define PLLDITHEN1 BIT(31)
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/* STM32_USBPHYC_MISC bit fields */
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#define SWITHOST BIT(0)
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/* STM32_USBPHYC_TUNE bit fields */
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#define INCURREN BIT(0)
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#define INCURRINT BIT(1)
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#define LFSCAPEN BIT(2)
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#define HSDRVSLEW BIT(3)
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#define HSDRVDCCUR BIT(4)
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#define HSDRVDCLEV BIT(5)
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#define HSDRVCURINCR BIT(6)
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#define FSDRVRFADJ BIT(7)
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#define HSDRVRFRED BIT(8)
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#define HSDRVCHKITRM GENMASK(12, 9)
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#define HSDRVCHKZTRM GENMASK(14, 13)
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#define OTPCOMP GENMASK(19, 15)
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#define SQLCHCTL GENMASK(21, 20)
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#define HDRXGNEQEN BIT(22)
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#define HSRXOFF GENMASK(24, 23)
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#define HSFALLPREEM BIT(25)
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#define SHTCCTCTLPROT BIT(26)
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#define STAGSEL BIT(27)
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#define MAX_PHYS 2
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/* max 100 us for PLL lock and 100 us for PHY init */
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#define PLL_INIT_TIME_US 200
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#define PLL_PWR_DOWN_TIME_US 5
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#define PLL_FVCO 2880 /* in MHz */
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#define PLL_INFF_MIN_RATE 19200000 /* in Hz */
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#define PLL_INFF_MAX_RATE 38400000 /* in Hz */
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/* USBPHYC_CLK48 */
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#define USBPHYC_CLK48_FREQ 48000000 /* in Hz */
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enum boosting_vals {
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BOOST_1000_UA = 1000,
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BOOST_2000_UA = 2000,
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};
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enum dc_level_vals {
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DC_MINUS_5_TO_7_MV,
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DC_PLUS_5_TO_7_MV,
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DC_PLUS_10_TO_14_MV,
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DC_MAX,
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};
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enum current_trim {
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CUR_NOMINAL,
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CUR_PLUS_1_56_PCT,
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CUR_PLUS_3_12_PCT,
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CUR_PLUS_4_68_PCT,
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CUR_PLUS_6_24_PCT,
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CUR_PLUS_7_8_PCT,
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CUR_PLUS_9_36_PCT,
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CUR_PLUS_10_92_PCT,
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CUR_PLUS_12_48_PCT,
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CUR_PLUS_14_04_PCT,
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CUR_PLUS_15_6_PCT,
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CUR_PLUS_17_16_PCT,
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CUR_PLUS_19_01_PCT,
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CUR_PLUS_20_58_PCT,
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CUR_PLUS_22_16_PCT,
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CUR_PLUS_23_73_PCT,
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CUR_MAX,
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};
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enum impedance_trim {
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IMP_NOMINAL,
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IMP_MINUS_2_OHMS,
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IMP_MINUS_4_OMHS,
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IMP_MINUS_6_OHMS,
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IMP_MAX,
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};
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enum squelch_level {
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SQLCH_NOMINAL,
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SQLCH_PLUS_7_MV,
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SQLCH_MINUS_5_MV,
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SQLCH_PLUS_14_MV,
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SQLCH_MAX,
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};
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enum rx_offset {
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NO_RX_OFFSET,
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RX_OFFSET_PLUS_5_MV,
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RX_OFFSET_PLUS_10_MV,
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RX_OFFSET_MINUS_5_MV,
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RX_OFFSET_MAX,
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};
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struct pll_params {
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u8 ndiv;
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u16 frac;
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};
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struct stm32_usbphyc {
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fdt_addr_t base;
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struct clk clk;
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struct udevice *vdda1v1;
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struct udevice *vdda1v8;
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struct stm32_usbphyc_phy {
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struct udevice *vdd;
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struct udevice *vbus;
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bool init;
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bool powered;
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} phys[MAX_PHYS];
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int n_pll_cons;
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};
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static void stm32_usbphyc_get_pll_params(u32 clk_rate,
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struct pll_params *pll_params)
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{
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unsigned long long fvco, ndiv, frac;
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/*
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* | FVCO = INFF*2*(NDIV + FRACT/2^16 ) when DITHER_DISABLE[1] = 1
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* | FVCO = 2880MHz
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* | NDIV = integer part of input bits to set the LDF
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* | FRACT = fractional part of input bits to set the LDF
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* => PLLNDIV = integer part of (FVCO / (INFF*2))
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* => PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
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* <=> PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
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*/
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fvco = (unsigned long long)PLL_FVCO * 1000000; /* In Hz */
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ndiv = fvco;
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do_div(ndiv, (clk_rate * 2));
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pll_params->ndiv = (u8)ndiv;
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frac = fvco * (1 << 16);
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do_div(frac, (clk_rate * 2));
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frac = frac - (ndiv * (1 << 16));
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pll_params->frac = (u16)frac;
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}
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static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
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{
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struct pll_params pll_params;
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u32 clk_rate = clk_get_rate(&usbphyc->clk);
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u32 usbphyc_pll;
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if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) {
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log_debug("input clk freq (%dHz) out of range\n",
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clk_rate);
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return -EINVAL;
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}
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stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
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usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP;
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usbphyc_pll |= ((pll_params.ndiv << PLLNDIV_SHIFT) & PLLNDIV);
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if (pll_params.frac) {
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usbphyc_pll |= PLLFRACCTL;
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usbphyc_pll |= ((pll_params.frac << PLLFRACIN_SHIFT)
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& PLLFRACIN);
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}
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writel(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
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log_debug("input clk freq=%dHz, ndiv=%d, frac=%d\n",
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clk_rate, pll_params.ndiv, pll_params.frac);
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return 0;
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}
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static bool stm32_usbphyc_is_powered(struct stm32_usbphyc *usbphyc)
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{
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int i;
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for (i = 0; i < MAX_PHYS; i++) {
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if (usbphyc->phys[i].powered)
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return true;
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}
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return false;
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}
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static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
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{
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bool pllen = readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN ?
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true : false;
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int ret;
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/* Check if one consumer has already configured the pll */
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if (pllen && usbphyc->n_pll_cons) {
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usbphyc->n_pll_cons++;
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return 0;
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}
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if (usbphyc->vdda1v1) {
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ret = regulator_set_enable(usbphyc->vdda1v1, true);
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if (ret)
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return ret;
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}
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if (usbphyc->vdda1v8) {
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ret = regulator_set_enable(usbphyc->vdda1v8, true);
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if (ret)
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return ret;
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}
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if (pllen) {
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clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
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udelay(PLL_PWR_DOWN_TIME_US);
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}
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ret = stm32_usbphyc_pll_init(usbphyc);
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if (ret)
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return ret;
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setbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
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/* We must wait PLL_INIT_TIME_US before using PHY */
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udelay(PLL_INIT_TIME_US);
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if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN))
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return -EIO;
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usbphyc->n_pll_cons++;
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return 0;
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}
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static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
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{
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int ret;
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usbphyc->n_pll_cons--;
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/* Check if other consumer requires pllen */
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if (usbphyc->n_pll_cons)
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return 0;
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clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
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/*
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* We must wait PLL_PWR_DOWN_TIME_US before checking that PLLEN
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* bit is still clear
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*/
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udelay(PLL_PWR_DOWN_TIME_US);
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if (readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN)
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return -EIO;
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if (usbphyc->vdda1v1) {
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ret = regulator_set_enable(usbphyc->vdda1v1, false);
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if (ret)
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return ret;
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}
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if (usbphyc->vdda1v8) {
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ret = regulator_set_enable(usbphyc->vdda1v8, false);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int stm32_usbphyc_phy_init(struct phy *phy)
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{
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struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
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struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
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int ret;
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dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
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if (usbphyc_phy->init)
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return 0;
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ret = stm32_usbphyc_pll_enable(usbphyc);
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if (ret)
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return log_ret(ret);
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usbphyc_phy->init = true;
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return 0;
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}
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static int stm32_usbphyc_phy_exit(struct phy *phy)
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{
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struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
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struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
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int ret;
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dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
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if (!usbphyc_phy->init)
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return 0;
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ret = stm32_usbphyc_pll_disable(usbphyc);
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usbphyc_phy->init = false;
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return log_ret(ret);
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}
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static int stm32_usbphyc_phy_power_on(struct phy *phy)
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{
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struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
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struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
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int ret;
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dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
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if (usbphyc_phy->vdd) {
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ret = regulator_set_enable(usbphyc_phy->vdd, true);
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if (ret)
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return ret;
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}
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if (usbphyc_phy->vbus) {
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ret = regulator_set_enable(usbphyc_phy->vbus, true);
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if (ret)
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return ret;
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}
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usbphyc_phy->powered = true;
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return 0;
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}
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static int stm32_usbphyc_phy_power_off(struct phy *phy)
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{
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struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
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struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
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int ret;
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dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
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usbphyc_phy->powered = false;
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if (stm32_usbphyc_is_powered(usbphyc))
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return 0;
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if (usbphyc_phy->vbus) {
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ret = regulator_set_enable_if_allowed(usbphyc_phy->vbus, false);
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if (ret)
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return ret;
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}
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if (usbphyc_phy->vdd) {
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ret = regulator_set_enable_if_allowed(usbphyc_phy->vdd, false);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int stm32_usbphyc_get_regulator(ofnode node,
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char *supply_name,
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struct udevice **regulator)
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{
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struct ofnode_phandle_args regulator_phandle;
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int ret;
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ret = ofnode_parse_phandle_with_args(node, supply_name,
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NULL, 0, 0,
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®ulator_phandle);
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if (ret)
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return ret;
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ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR,
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regulator_phandle.node,
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regulator);
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if (ret)
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return ret;
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return 0;
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}
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static int stm32_usbphyc_of_xlate(struct phy *phy,
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struct ofnode_phandle_args *args)
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{
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if (args->args_count < 1)
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return -ENODEV;
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if (args->args[0] >= MAX_PHYS)
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return -ENODEV;
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phy->id = args->args[0];
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if ((phy->id == 0 && args->args_count != 1) ||
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(phy->id == 1 && args->args_count != 2)) {
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dev_err(phy->dev, "invalid number of cells for phy port%ld\n",
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phy->id);
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return -EINVAL;
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}
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return 0;
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}
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static void stm32_usbphyc_tuning(struct udevice *dev, ofnode node, u32 index)
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{
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struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
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u32 reg = STM32_USBPHYC_TUNE(index);
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u32 otpcomp, val, tune = 0;
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int ret;
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/* Backup OTP compensation code */
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otpcomp = FIELD_GET(OTPCOMP, readl(usbphyc->base + reg));
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ret = ofnode_read_u32(node, "st,current-boost-microamp", &val);
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if (!ret && (val == BOOST_1000_UA || val == BOOST_2000_UA)) {
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val = (val == BOOST_2000_UA) ? 1 : 0;
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tune |= INCURREN | FIELD_PREP(INCURRINT, val);
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} else if (ret != -EINVAL) {
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dev_warn(dev, "phy%d: invalid st,current-boost-microamp value\n", index);
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}
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if (!ofnode_read_bool(node, "st,no-lsfs-fb-cap"))
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tune |= LFSCAPEN;
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if (ofnode_read_bool(node, "st,decrease-hs-slew-rate"))
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tune |= HSDRVSLEW;
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ret = ofnode_read_u32(node, "st,tune-hs-dc-level", &val);
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if (!ret && val < DC_MAX) {
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if (val == DC_MINUS_5_TO_7_MV) {
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tune |= HSDRVDCCUR;
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} else {
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val = (val == DC_PLUS_10_TO_14_MV) ? 1 : 0;
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tune |= HSDRVCURINCR | FIELD_PREP(HSDRVDCLEV, val);
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}
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} else if (ret != -EINVAL) {
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dev_warn(dev, "phy%d: invalid st,tune-hs-dc-level value\n", index);
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}
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if (ofnode_read_bool(node, "st,enable-fs-rftime-tuning"))
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tune |= FSDRVRFADJ;
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if (ofnode_read_bool(node, "st,enable-hs-rftime-reduction"))
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tune |= HSDRVRFRED;
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ret = ofnode_read_u32(node, "st,trim-hs-current", &val);
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if (!ret && val < CUR_MAX)
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tune |= FIELD_PREP(HSDRVCHKITRM, val);
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else if (ret != -EINVAL)
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dev_warn(dev, "phy%d: invalid st,trim-hs-current value\n", index);
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ret = ofnode_read_u32(node, "st,trim-hs-impedance", &val);
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if (!ret && val < IMP_MAX)
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tune |= FIELD_PREP(HSDRVCHKZTRM, val);
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else if (ret != -EINVAL)
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dev_warn(dev, "phy%d: invalid trim-hs-impedance value\n", index);
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ret = ofnode_read_u32(node, "st,tune-squelch-level", &val);
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if (!ret && val < SQLCH_MAX)
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tune |= FIELD_PREP(SQLCHCTL, val);
|
|
else if (ret != -EINVAL)
|
|
dev_warn(dev, "phy%d: invalid st,tune-squelch-level value\n", index);
|
|
|
|
if (ofnode_read_bool(node, "st,enable-hs-rx-gain-eq"))
|
|
tune |= HDRXGNEQEN;
|
|
|
|
ret = ofnode_read_u32(node, "st,tune-hs-rx-offset", &val);
|
|
if (!ret && val < RX_OFFSET_MAX)
|
|
tune |= FIELD_PREP(HSRXOFF, val);
|
|
else if (ret != -EINVAL)
|
|
dev_warn(dev, "phy%d: invalid st,tune-hs-rx-offset value\n", index);
|
|
|
|
if (ofnode_read_bool(node, "st,no-hs-ftime-ctrl"))
|
|
tune |= HSFALLPREEM;
|
|
|
|
if (!ofnode_read_bool(node, "st,no-lsfs-sc"))
|
|
tune |= SHTCCTCTLPROT;
|
|
|
|
if (ofnode_read_bool(node, "st,enable-hs-tx-staggering"))
|
|
tune |= STAGSEL;
|
|
|
|
/* Restore OTP compensation code */
|
|
tune |= FIELD_PREP(OTPCOMP, otpcomp);
|
|
|
|
writel(tune, usbphyc->base + reg);
|
|
}
|
|
|
|
static const struct phy_ops stm32_usbphyc_phy_ops = {
|
|
.init = stm32_usbphyc_phy_init,
|
|
.exit = stm32_usbphyc_phy_exit,
|
|
.power_on = stm32_usbphyc_phy_power_on,
|
|
.power_off = stm32_usbphyc_phy_power_off,
|
|
.of_xlate = stm32_usbphyc_of_xlate,
|
|
};
|
|
|
|
static int stm32_usbphyc_bind(struct udevice *dev)
|
|
{
|
|
int ret;
|
|
|
|
ret = device_bind_driver_to_node(dev, "stm32-usbphyc-clk", "ck_usbo_48m",
|
|
dev_ofnode(dev), NULL);
|
|
|
|
return log_ret(ret);
|
|
}
|
|
|
|
static int stm32_usbphyc_probe(struct udevice *dev)
|
|
{
|
|
struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
|
|
struct reset_ctl reset;
|
|
ofnode node, connector;
|
|
int ret;
|
|
|
|
usbphyc->base = dev_read_addr(dev);
|
|
if (usbphyc->base == FDT_ADDR_T_NONE)
|
|
return -EINVAL;
|
|
|
|
/* Enable clock */
|
|
ret = clk_get_by_index(dev, 0, &usbphyc->clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = clk_enable(&usbphyc->clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Reset */
|
|
ret = reset_get_by_index(dev, 0, &reset);
|
|
if (!ret) {
|
|
reset_assert(&reset);
|
|
udelay(2);
|
|
reset_deassert(&reset);
|
|
}
|
|
|
|
/* get usbphyc regulator */
|
|
ret = device_get_supply_regulator(dev, "vdda1v1-supply",
|
|
&usbphyc->vdda1v1);
|
|
if (ret) {
|
|
dev_err(dev, "Can't get vdda1v1-supply regulator\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = device_get_supply_regulator(dev, "vdda1v8-supply",
|
|
&usbphyc->vdda1v8);
|
|
if (ret) {
|
|
dev_err(dev, "Can't get vdda1v8-supply regulator\n");
|
|
return ret;
|
|
}
|
|
|
|
/* parse all PHY subnodes to populate regulator associated to each PHY port */
|
|
dev_for_each_subnode(node, dev) {
|
|
fdt_addr_t phy_id;
|
|
struct stm32_usbphyc_phy *usbphyc_phy;
|
|
|
|
phy_id = ofnode_read_u32_default(node, "reg", FDT_ADDR_T_NONE);
|
|
if (phy_id >= MAX_PHYS) {
|
|
dev_err(dev, "invalid reg value %llx for %s\n",
|
|
(fdt64_t)phy_id, ofnode_get_name(node));
|
|
return -ENOENT;
|
|
}
|
|
|
|
/* Configure phy tuning */
|
|
stm32_usbphyc_tuning(dev, node, phy_id);
|
|
|
|
usbphyc_phy = usbphyc->phys + phy_id;
|
|
usbphyc_phy->init = false;
|
|
usbphyc_phy->powered = false;
|
|
ret = stm32_usbphyc_get_regulator(node, "phy-supply",
|
|
&usbphyc_phy->vdd);
|
|
if (ret) {
|
|
dev_err(dev, "Can't get phy-supply regulator\n");
|
|
return ret;
|
|
}
|
|
|
|
usbphyc_phy->vbus = NULL;
|
|
connector = ofnode_find_subnode(node, "connector");
|
|
if (ofnode_valid(connector)) {
|
|
ret = stm32_usbphyc_get_regulator(connector, "vbus-supply",
|
|
&usbphyc_phy->vbus);
|
|
}
|
|
}
|
|
|
|
/* Check if second port has to be used for host controller */
|
|
if (dev_read_bool(dev, "st,port2-switch-to-host"))
|
|
setbits_le32(usbphyc->base + STM32_USBPHYC_MISC, SWITHOST);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id stm32_usbphyc_of_match[] = {
|
|
{ .compatible = "st,stm32mp1-usbphyc", },
|
|
{ },
|
|
};
|
|
|
|
U_BOOT_DRIVER(stm32_usb_phyc) = {
|
|
.name = "stm32-usbphyc",
|
|
.id = UCLASS_PHY,
|
|
.of_match = stm32_usbphyc_of_match,
|
|
.ops = &stm32_usbphyc_phy_ops,
|
|
.bind = stm32_usbphyc_bind,
|
|
.probe = stm32_usbphyc_probe,
|
|
.priv_auto = sizeof(struct stm32_usbphyc),
|
|
};
|
|
|
|
struct stm32_usbphyc_clk {
|
|
bool enable;
|
|
};
|
|
|
|
static ulong stm32_usbphyc_clk48_get_rate(struct clk *clk)
|
|
{
|
|
return USBPHYC_CLK48_FREQ;
|
|
}
|
|
|
|
static int stm32_usbphyc_clk48_enable(struct clk *clk)
|
|
{
|
|
struct stm32_usbphyc_clk *usbphyc_clk = dev_get_priv(clk->dev);
|
|
struct stm32_usbphyc *usbphyc;
|
|
int ret;
|
|
|
|
if (usbphyc_clk->enable)
|
|
return 0;
|
|
|
|
usbphyc = dev_get_priv(clk->dev->parent);
|
|
|
|
/* ck_usbo_48m is generated by usbphyc PLL */
|
|
ret = stm32_usbphyc_pll_enable(usbphyc);
|
|
if (ret)
|
|
return ret;
|
|
|
|
usbphyc_clk->enable = true;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_usbphyc_clk48_disable(struct clk *clk)
|
|
{
|
|
struct stm32_usbphyc_clk *usbphyc_clk = dev_get_priv(clk->dev);
|
|
struct stm32_usbphyc *usbphyc;
|
|
int ret;
|
|
|
|
if (!usbphyc_clk->enable)
|
|
return 0;
|
|
|
|
usbphyc = dev_get_priv(clk->dev->parent);
|
|
|
|
ret = stm32_usbphyc_pll_disable(usbphyc);
|
|
if (ret)
|
|
return ret;
|
|
|
|
usbphyc_clk->enable = false;
|
|
|
|
return 0;
|
|
}
|
|
|
|
const struct clk_ops usbphyc_clk48_ops = {
|
|
.get_rate = stm32_usbphyc_clk48_get_rate,
|
|
.enable = stm32_usbphyc_clk48_enable,
|
|
.disable = stm32_usbphyc_clk48_disable,
|
|
};
|
|
|
|
U_BOOT_DRIVER(stm32_usb_phyc_clk) = {
|
|
.name = "stm32-usbphyc-clk",
|
|
.id = UCLASS_CLK,
|
|
.ops = &usbphyc_clk48_ops,
|
|
.priv_auto = sizeof(struct stm32_usbphyc_clk),
|
|
};
|