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caa4daa2ae
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
177 lines
4.4 KiB
C
177 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Broadcom
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*/
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#include <common.h>
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#include <dm.h>
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#include <generic-phy.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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/* we have up to 8 PAXB based RC. The 9th one is always PAXC */
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#define SR_NR_PCIE_PHYS 8
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#define PCIE_PIPEMUX_CFG_OFFSET 0x10c
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#define PCIE_PIPEMUX_SELECT_STRAP GENMASK(3, 0)
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#define CDRU_STRAP_DATA_LSW_OFFSET 0x5c
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#define PCIE_PIPEMUX_SHIFT 19
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#define PCIE_PIPEMUX_MASK GENMASK(3, 0)
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/**
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* struct sr_pcie_phy_core - Stingray PCIe PHY core control
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*
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* @dev: pointer to device
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* @base: base register of PCIe SS
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* @cdru: CDRU base address
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* @pipemux: pipemuex strap
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*/
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struct sr_pcie_phy_core {
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struct udevice *dev;
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void __iomem *base;
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void __iomem *cdru;
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u32 pipemux;
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};
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/*
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* PCIe PIPEMUX lookup table
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*
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* Each array index represents a PIPEMUX strap setting
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* The array element represents a bitmap where a set bit means the PCIe
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* core and associated serdes has been enabled as RC and is available for use
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*/
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static const u8 pipemux_table[] = {
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/* PIPEMUX = 0, EP 1x16 */
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0x00,
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/* PIPEMUX = 1, EP 1x8 + RC 1x8, core 7 */
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0x80,
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/* PIPEMUX = 2, EP 4x4 */
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0x00,
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/* PIPEMUX = 3, RC 2x8, cores 0, 7 */
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0x81,
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/* PIPEMUX = 4, RC 4x4, cores 0, 1, 6, 7 */
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0xc3,
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/* PIPEMUX = 5, RC 8x2, all 8 cores */
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0xff,
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/* PIPEMUX = 6, RC 3x4 + 2x2, cores 0, 2, 3, 6, 7 */
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0xcd,
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/* PIPEMUX = 7, RC 1x4 + 6x2, cores 0, 2, 3, 4, 5, 6, 7 */
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0xfd,
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/* PIPEMUX = 8, EP 1x8 + RC 4x2, cores 4, 5, 6, 7 */
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0xf0,
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/* PIPEMUX = 9, EP 1x8 + RC 2x4, cores 6, 7 */
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0xc0,
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/* PIPEMUX = 10, EP 2x4 + RC 2x4, cores 1, 6 */
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0x42,
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/* PIPEMUX = 11, EP 2x4 + RC 4x2, cores 2, 3, 4, 5 */
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0x3c,
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/* PIPEMUX = 12, EP 1x4 + RC 6x2, cores 2, 3, 4, 5, 6, 7 */
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0xfc,
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/* PIPEMUX = 13, RC 2x4 + RC 1x4 + 2x2, cores 2, 3, 6 */
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0x4c,
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};
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/*
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* Return true if the strap setting is valid
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*/
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static bool pipemux_strap_is_valid(u32 pipemux)
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{
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return !!(pipemux < ARRAY_SIZE(pipemux_table));
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}
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/*
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* Read the PCIe PIPEMUX from strap
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*/
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static u32 pipemux_strap_read(struct sr_pcie_phy_core *core)
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{
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u32 pipemux;
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/*
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* Read PIPEMUX configuration register to determine the pipemux setting
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*
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* In the case when the value indicates using HW strap, fall back to
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* use HW strap
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*/
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pipemux = readl(core->base + PCIE_PIPEMUX_CFG_OFFSET);
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pipemux &= PCIE_PIPEMUX_MASK;
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if (pipemux == PCIE_PIPEMUX_SELECT_STRAP) {
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pipemux = readl(core->cdru + CDRU_STRAP_DATA_LSW_OFFSET);
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pipemux >>= PCIE_PIPEMUX_SHIFT;
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pipemux &= PCIE_PIPEMUX_MASK;
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}
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return pipemux;
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}
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static int sr_pcie_phy_init(struct phy *phy)
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{
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struct sr_pcie_phy_core *core = dev_get_priv(phy->dev);
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unsigned int core_idx = phy->id;
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debug("%s %lx\n", __func__, phy->id);
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/*
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* Check whether this PHY is for root complex or not. If yes, return
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* zero so the host driver can proceed to enumeration. If not, return
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* an error and that will force the host driver to bail out
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*/
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if (!!((pipemux_table[core->pipemux] >> core_idx) & 0x1))
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return 0;
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return -ENODEV;
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}
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static int sr_pcie_phy_xlate(struct phy *phy, struct ofnode_phandle_args *args)
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{
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debug("%s %d\n", __func__, args->args[0]);
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if (args->args_count && args->args[0] < SR_NR_PCIE_PHYS)
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phy->id = args->args[0];
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else
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return -ENODEV;
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return 0;
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}
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static const struct phy_ops sr_pcie_phy_ops = {
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.of_xlate = sr_pcie_phy_xlate,
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.init = sr_pcie_phy_init,
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};
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static int sr_pcie_phy_probe(struct udevice *dev)
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{
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struct sr_pcie_phy_core *core = dev_get_priv(dev);
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core->dev = dev;
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core->base = (void __iomem *)devfdt_get_addr_name(dev, "reg_base");
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core->cdru = (void __iomem *)devfdt_get_addr_name(dev, "cdru_base");
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debug("ip base %p\n", core->base);
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debug("cdru base %p\n", core->cdru);
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/* read the PCIe PIPEMUX strap setting */
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core->pipemux = pipemux_strap_read(core);
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if (!pipemux_strap_is_valid(core->pipemux)) {
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pr_err("invalid PCIe PIPEMUX strap %u\n", core->pipemux);
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return -EIO;
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}
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debug("%s %#x\n", __func__, core->pipemux);
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pr_info("Stingray PCIe PHY driver initialized\n");
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return 0;
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}
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static const struct udevice_id sr_pcie_phy_match_table[] = {
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{ .compatible = "brcm,sr-pcie-phy" },
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{ }
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};
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U_BOOT_DRIVER(sr_pcie_phy) = {
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.name = "sr-pcie-phy",
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.id = UCLASS_PHY,
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.probe = sr_pcie_phy_probe,
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.of_match = sr_pcie_phy_match_table,
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.ops = &sr_pcie_phy_ops,
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.plat_auto = sizeof(struct sr_pcie_phy_core),
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.priv_auto = sizeof(struct sr_pcie_phy_core),
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};
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