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41575d8e4c
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
252 lines
5.6 KiB
C
252 lines
5.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Stefan Roese <sr@denx.de>
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*
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* Derived from linux/drivers/phy/ralink/phy-ralink-usb.c
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* Copyright (C) 2017 John Crispin <john@phrozen.org>
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <generic-phy.h>
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#include <log.h>
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#include <reset.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#define OFS_U2_PHY_AC0 0x800
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#define USBPLL_FBDIV_S 16
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#define USBPLL_FBDIV_M GENMASK(22, 16)
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#define BG_TRIM_S 8
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#define BG_TRIM_M GENMASK(11, 8)
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#define BG_RBSEL_S 6
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#define BG_RBSEL_M GENMASK(7, 6)
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#define BG_RASEL_S 4
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#define BG_RASEL_M GENMASK(5, 4)
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#define BGR_DIV_S 2
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#define BGR_DIV_M GENMASK(3, 2)
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#define CHP_EN BIT(1)
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#define OFS_U2_PHY_AC1 0x804
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#define VRT_VREF_SEL_S 28
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#define VRT_VREF_SEL_M GENMASK(30, 28)
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#define TERM_VREF_SEL_S 24
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#define TERM_VREF_SEL_M GENMASK(26, 24)
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#define USBPLL_RSVD BIT(4)
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#define USBPLL_ACCEN BIT(3)
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#define USBPLL_LF BIT(2)
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#define OFS_U2_PHY_AC2 0x808
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#define OFS_U2_PHY_ACR0 0x810
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#define HSTX_SRCAL_EN BIT(23)
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#define HSTX_SRCTRL_S 16
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#define HSTX_SRCTRL_M GENMASK(18, 16)
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#define OFS_U2_PHY_ACR3 0x81C
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#define HSTX_DBIST_S 28
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#define HSTX_DBIST_M GENMASK(31, 28)
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#define HSRX_BIAS_EN_SEL_S 20
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#define HSRX_BIAS_EN_SEL_M GENMASK(21, 20)
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#define OFS_U2_PHY_DCR0 0x860
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#define PHYD_RESERVE_S 8
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#define PHYD_RESERVE_M GENMASK(23, 8)
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#define CDR_FILT_S 0
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#define CDR_FILT_M GENMASK(3, 0)
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#define OFS_U2_PHY_DTM0 0x868
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#define FORCE_USB_CLKEN BIT(25)
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#define OFS_FM_CR0 0xf00
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#define FREQDET_EN BIT(24)
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#define CYCLECNT_S 0
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#define CYCLECNT_M GENMASK(23, 0)
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#define OFS_FM_MONR0 0xf0c
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#define OFS_FM_MONR1 0xf10
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#define FRCK_EN BIT(8)
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#define U2_SR_COEF_7628 32
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struct mt76x8_usb_phy {
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void __iomem *base;
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struct clk cg; /* for clock gating */
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struct reset_ctl rst_phy;
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};
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static void phy_w32(struct mt76x8_usb_phy *phy, u32 reg, u32 val)
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{
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writel(val, phy->base + reg);
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}
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static u32 phy_r32(struct mt76x8_usb_phy *phy, u32 reg)
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{
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return readl(phy->base + reg);
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}
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static void phy_rmw32(struct mt76x8_usb_phy *phy, u32 reg, u32 clr, u32 set)
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{
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clrsetbits_32(phy->base + reg, clr, set);
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}
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static void mt76x8_usb_phy_init(struct mt76x8_usb_phy *phy)
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{
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phy_r32(phy, OFS_U2_PHY_AC2);
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phy_r32(phy, OFS_U2_PHY_ACR0);
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phy_r32(phy, OFS_U2_PHY_DCR0);
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phy_w32(phy, OFS_U2_PHY_DCR0,
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(0xffff << PHYD_RESERVE_S) | (2 << CDR_FILT_S));
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phy_r32(phy, OFS_U2_PHY_DCR0);
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phy_w32(phy, OFS_U2_PHY_DCR0,
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(0x5555 << PHYD_RESERVE_S) | (2 << CDR_FILT_S));
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phy_r32(phy, OFS_U2_PHY_DCR0);
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phy_w32(phy, OFS_U2_PHY_DCR0,
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(0xaaaa << PHYD_RESERVE_S) | (2 << CDR_FILT_S));
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phy_r32(phy, OFS_U2_PHY_DCR0);
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phy_w32(phy, OFS_U2_PHY_DCR0,
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(4 << PHYD_RESERVE_S) | (2 << CDR_FILT_S));
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phy_r32(phy, OFS_U2_PHY_DCR0);
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phy_w32(phy, OFS_U2_PHY_AC0,
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(0x48 << USBPLL_FBDIV_S) | (8 << BG_TRIM_S) |
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(1 << BG_RBSEL_S) | (2 << BG_RASEL_S) | (2 << BGR_DIV_S) |
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CHP_EN);
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phy_w32(phy, OFS_U2_PHY_AC1,
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(4 << VRT_VREF_SEL_S) | (4 << TERM_VREF_SEL_S) | USBPLL_RSVD |
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USBPLL_ACCEN | USBPLL_LF);
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phy_w32(phy, OFS_U2_PHY_ACR3,
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(12 << HSTX_DBIST_S) | (2 << HSRX_BIAS_EN_SEL_S));
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phy_w32(phy, OFS_U2_PHY_DTM0, FORCE_USB_CLKEN);
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}
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static void mt76x8_usb_phy_sr_calibrate(struct mt76x8_usb_phy *phy)
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{
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u32 fmout, tmp = 4;
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int i;
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/* Enable HS TX SR calibration */
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phy_rmw32(phy, OFS_U2_PHY_ACR0, 0, HSTX_SRCAL_EN);
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mdelay(1);
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/* Enable free run clock */
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phy_rmw32(phy, OFS_FM_MONR1, 0, FRCK_EN);
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/* Set cycle count = 0x400 */
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phy_rmw32(phy, OFS_FM_CR0, CYCLECNT_M, 0x400 << CYCLECNT_S);
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/* Enable frequency meter */
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phy_rmw32(phy, OFS_FM_CR0, 0, FREQDET_EN);
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/* Wait for FM detection done, set timeout to 10ms */
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for (i = 0; i < 10; i++) {
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fmout = phy_r32(phy, OFS_FM_MONR0);
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if (fmout)
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break;
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mdelay(1);
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}
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/* Disable frequency meter */
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phy_rmw32(phy, OFS_FM_CR0, FREQDET_EN, 0);
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/* Disable free run clock */
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phy_rmw32(phy, OFS_FM_MONR1, FRCK_EN, 0);
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/* Disable HS TX SR calibration */
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phy_rmw32(phy, OFS_U2_PHY_ACR0, HSTX_SRCAL_EN, 0);
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mdelay(1);
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if (fmout) {
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/*
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* set reg = (1024 / FM_OUT) * 25 * 0.028
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* (round to the nearest digits)
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*/
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tmp = (((1024 * 25 * U2_SR_COEF_7628) / fmout) + 500) / 1000;
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}
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phy_rmw32(phy, OFS_U2_PHY_ACR0, HSTX_SRCTRL_M,
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(tmp << HSTX_SRCTRL_S) & HSTX_SRCTRL_M);
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}
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static int mt76x8_usb_phy_power_on(struct phy *_phy)
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{
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struct mt76x8_usb_phy *phy = dev_get_priv(_phy->dev);
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clk_enable(&phy->cg);
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reset_deassert(&phy->rst_phy);
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/*
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* The SDK kernel had a delay of 100ms. however on device
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* testing showed that 10ms is enough
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*/
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mdelay(10);
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mt76x8_usb_phy_init(phy);
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mt76x8_usb_phy_sr_calibrate(phy);
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return 0;
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}
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static int mt76x8_usb_phy_power_off(struct phy *_phy)
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{
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struct mt76x8_usb_phy *phy = dev_get_priv(_phy->dev);
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clk_disable(&phy->cg);
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reset_assert(&phy->rst_phy);
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return 0;
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}
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static int mt76x8_usb_phy_probe(struct udevice *dev)
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{
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struct mt76x8_usb_phy *phy = dev_get_priv(dev);
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int ret;
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phy->base = dev_read_addr_ptr(dev);
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if (!phy->base)
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return -EINVAL;
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/* clock gate */
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ret = clk_get_by_name(dev, "cg", &phy->cg);
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if (ret)
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return ret;
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ret = reset_get_by_name(dev, "phy", &phy->rst_phy);
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if (ret)
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return ret;
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return 0;
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}
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static struct phy_ops mt76x8_usb_phy_ops = {
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.power_on = mt76x8_usb_phy_power_on,
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.power_off = mt76x8_usb_phy_power_off,
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};
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static const struct udevice_id mt76x8_usb_phy_ids[] = {
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{ .compatible = "mediatek,mt7628-usbphy" },
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{ }
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};
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U_BOOT_DRIVER(mt76x8_usb_phy) = {
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.name = "mt76x8_usb_phy",
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.id = UCLASS_PHY,
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.of_match = mt76x8_usb_phy_ids,
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.ops = &mt76x8_usb_phy_ops,
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.probe = mt76x8_usb_phy_probe,
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.priv_auto = sizeof(struct mt76x8_usb_phy),
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};
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