mirror of
https://github.com/AsahiLinux/u-boot
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a3f1eaa793
With commit84a42ae366
("dm: core: Rename device node to indicate it is private") and commitf10643cf8a
("dm: core: Access device ofnode through functions") accesses to the "node" member were replaced with dev_ofnode(). Also apply that replacement here. Fixes:4547551aa0
("phy: Add Amlogic AXG MIPI PCIe Analog PHY driver") Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
233 lines
6.1 KiB
C
233 lines
6.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Amlogic AXG MIPI + PCIE analog PHY driver
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*
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* Copyright (C) 2019 Remi Pommarel <repk@triplefau.lt>
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* Copyright (C) 2020 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include <common.h>
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#include <log.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <bitfield.h>
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#include <dm.h>
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#include <errno.h>
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#include <generic-phy.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <linux/delay.h>
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#include <power/regulator.h>
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#include <reset.h>
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#include <clk.h>
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#include <phy-mipi-dphy.h>
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#include <linux/bitops.h>
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#include <linux/compat.h>
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#include <linux/bitfield.h>
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#define HHI_MIPI_CNTL0 0x00
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#define HHI_MIPI_CNTL0_COMMON_BLOCK GENMASK(31, 28)
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#define HHI_MIPI_CNTL0_ENABLE BIT(29)
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#define HHI_MIPI_CNTL0_BANDGAP BIT(26)
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#define HHI_MIPI_CNTL0_DIF_REF_CTL1 GENMASK(25, 16)
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#define HHI_MIPI_CNTL0_DIF_REF_CTL0 GENMASK(15, 0)
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#define HHI_MIPI_CNTL1 0x04
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#define HHI_MIPI_CNTL1_CH0_CML_PDR_EN BIT(12)
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#define HHI_MIPI_CNTL1_LP_ABILITY GENMASK(5, 4)
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#define HHI_MIPI_CNTL1_LP_RESISTER BIT(3)
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#define HHI_MIPI_CNTL1_INPUT_SETTING BIT(2)
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#define HHI_MIPI_CNTL1_INPUT_SEL BIT(1)
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#define HHI_MIPI_CNTL1_PRBS7_EN BIT(0)
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#define HHI_MIPI_CNTL2 0x08
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#define HHI_MIPI_CNTL2_CH_PU GENMASK(31, 25)
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#define HHI_MIPI_CNTL2_CH_CTL GENMASK(24, 19)
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#define HHI_MIPI_CNTL2_CH0_DIGDR_EN BIT(18)
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#define HHI_MIPI_CNTL2_CH_DIGDR_EN BIT(17)
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#define HHI_MIPI_CNTL2_LPULPS_EN BIT(16)
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#define HHI_MIPI_CNTL2_CH_EN GENMASK(15, 11)
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#define HHI_MIPI_CNTL2_CH0_LP_CTL GENMASK(10, 1)
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#define DSI_LANE_0 (1 << 4)
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#define DSI_LANE_1 (1 << 3)
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#define DSI_LANE_CLK (1 << 2)
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#define DSI_LANE_2 (1 << 1)
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#define DSI_LANE_3 (1 << 0)
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#define DSI_LANE_MASK (0x1F)
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struct phy_meson_axg_mipi_pcie_analog_priv {
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struct regmap *regmap;
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struct phy_configure_opts_mipi_dphy config;
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bool dsi_configured;
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bool dsi_enabled;
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bool powered;
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};
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static void phy_bandgap_enable(struct phy_meson_axg_mipi_pcie_analog_priv *priv)
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{
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regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
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HHI_MIPI_CNTL0_BANDGAP, HHI_MIPI_CNTL0_BANDGAP);
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regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
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HHI_MIPI_CNTL0_ENABLE, HHI_MIPI_CNTL0_ENABLE);
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}
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static void phy_bandgap_disable(struct phy_meson_axg_mipi_pcie_analog_priv *priv)
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{
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regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
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HHI_MIPI_CNTL0_BANDGAP, 0);
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regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
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HHI_MIPI_CNTL0_ENABLE, 0);
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}
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static void phy_dsi_analog_enable(struct phy_meson_axg_mipi_pcie_analog_priv *priv)
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{
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u32 reg;
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regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
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HHI_MIPI_CNTL0_DIF_REF_CTL1,
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FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL1, 0x1b8));
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regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
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BIT(31), BIT(31));
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regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
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HHI_MIPI_CNTL0_DIF_REF_CTL0,
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FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL0, 0x8));
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regmap_write(priv->regmap, HHI_MIPI_CNTL1, 0x001e);
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regmap_write(priv->regmap, HHI_MIPI_CNTL2,
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(0x26e0 << 16) | (0x459 << 0));
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reg = DSI_LANE_CLK;
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switch (priv->config.lanes) {
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case 4:
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reg |= DSI_LANE_3;
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fallthrough;
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case 3:
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reg |= DSI_LANE_2;
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fallthrough;
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case 2:
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reg |= DSI_LANE_1;
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fallthrough;
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case 1:
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reg |= DSI_LANE_0;
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break;
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default:
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reg = 0;
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}
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regmap_update_bits(priv->regmap, HHI_MIPI_CNTL2,
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HHI_MIPI_CNTL2_CH_EN,
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FIELD_PREP(HHI_MIPI_CNTL2_CH_EN, reg));
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priv->dsi_enabled = true;
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}
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static void phy_dsi_analog_disable(struct phy_meson_axg_mipi_pcie_analog_priv *priv)
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{
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regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
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HHI_MIPI_CNTL0_DIF_REF_CTL1,
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FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL1, 0));
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regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0, BIT(31), 0);
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regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
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HHI_MIPI_CNTL0_DIF_REF_CTL1, 0);
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regmap_write(priv->regmap, HHI_MIPI_CNTL1, 0x6);
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regmap_write(priv->regmap, HHI_MIPI_CNTL2, 0x00200000);
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priv->dsi_enabled = false;
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}
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static int phy_meson_axg_mipi_pcie_analog_configure(struct phy *phy, void *params)
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{
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struct udevice *dev = phy->dev;
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struct phy_meson_axg_mipi_pcie_analog_priv *priv = dev_get_priv(dev);
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struct phy_configure_opts_mipi_dphy *config = params;
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int ret;
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ret = phy_mipi_dphy_config_validate(config);
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if (ret)
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return ret;
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memcpy(&priv->config, config, sizeof(priv->config));
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priv->dsi_configured = true;
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/* If PHY was already powered on, setup the DSI analog part */
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if (priv->powered) {
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/* If reconfiguring, disable & reconfigure */
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if (priv->dsi_enabled)
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phy_dsi_analog_disable(priv);
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udelay(100);
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phy_dsi_analog_enable(priv);
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}
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return 0;
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}
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static int phy_meson_axg_mipi_pcie_analog_power_on(struct phy *phy)
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{
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struct udevice *dev = phy->dev;
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struct phy_meson_axg_mipi_pcie_analog_priv *priv = dev_get_priv(dev);
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phy_bandgap_enable(priv);
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if (priv->dsi_configured)
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phy_dsi_analog_enable(priv);
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priv->powered = true;
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return 0;
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}
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static int phy_meson_axg_mipi_pcie_analog_power_off(struct phy *phy)
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{
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struct udevice *dev = phy->dev;
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struct phy_meson_axg_mipi_pcie_analog_priv *priv = dev_get_priv(dev);
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phy_bandgap_disable(priv);
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if (priv->dsi_enabled)
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phy_dsi_analog_disable(priv);
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priv->powered = false;
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return 0;
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}
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struct phy_ops meson_axg_mipi_pcie_analog_ops = {
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.power_on = phy_meson_axg_mipi_pcie_analog_power_on,
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.power_off = phy_meson_axg_mipi_pcie_analog_power_off,
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.configure = phy_meson_axg_mipi_pcie_analog_configure,
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};
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int meson_axg_mipi_pcie_analog_probe(struct udevice *dev)
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{
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struct phy_meson_axg_mipi_pcie_analog_priv *priv = dev_get_priv(dev);
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priv->regmap = syscon_node_to_regmap(dev_ofnode(dev_get_parent(dev)));
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if (IS_ERR(priv->regmap))
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return PTR_ERR(priv->regmap);
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return 0;
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}
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static const struct udevice_id meson_axg_mipi_pcie_analog_ids[] = {
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{ .compatible = "amlogic,axg-mipi-pcie-analog-phy" },
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{ }
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};
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U_BOOT_DRIVER(meson_axg_mipi_pcie_analog) = {
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.name = "meson_axg_mipi_pcie_analog",
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.id = UCLASS_PHY,
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.of_match = meson_axg_mipi_pcie_analog_ids,
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.probe = meson_axg_mipi_pcie_analog_probe,
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.ops = &meson_axg_mipi_pcie_analog_ops,
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.priv_auto = sizeof(struct phy_meson_axg_mipi_pcie_analog_priv),
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};
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