mirror of
https://github.com/AsahiLinux/u-boot
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a12a73b664
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use dev_read_addr_ptr instead of the dev_read_addr function in the various files in the drivers directory that cast to a pointer. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
530 lines
13 KiB
C
530 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Copyright (c) 2010-2011 NVIDIA Corporation
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* NVIDIA Corporation <www.nvidia.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <i2c.h>
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#include <log.h>
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#include <asm/io.h>
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#include <clk.h>
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#include <reset.h>
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#ifndef CONFIG_TEGRA186
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#include <asm/arch/clock.h>
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#include <asm/arch/funcmux.h>
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#endif
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#include <asm/arch/gpio.h>
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#include <asm/arch-tegra/tegra_i2c.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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enum i2c_type {
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TYPE_114,
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TYPE_STD,
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TYPE_DVC,
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};
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/* Information about i2c controller */
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struct i2c_bus {
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int id;
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struct reset_ctl reset_ctl;
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struct clk clk;
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int speed;
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int pinmux_config;
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struct i2c_control *control;
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struct i2c_ctlr *regs;
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enum i2c_type type;
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int inited; /* bus is inited */
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};
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static void set_packet_mode(struct i2c_bus *i2c_bus)
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{
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u32 config;
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config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK;
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if (i2c_bus->type == TYPE_DVC) {
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struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
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writel(config, &dvc->cnfg);
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} else {
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writel(config, &i2c_bus->regs->cnfg);
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/*
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* program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe
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* issues, i.e., some slaves may be wrongly detected.
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*/
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setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK);
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}
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}
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static void i2c_reset_controller(struct i2c_bus *i2c_bus)
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{
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/* Reset I2C controller. */
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reset_assert(&i2c_bus->reset_ctl);
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udelay(1);
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reset_deassert(&i2c_bus->reset_ctl);
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udelay(1);
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/* re-program config register to packet mode */
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set_packet_mode(i2c_bus);
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}
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static int i2c_init_clock(struct i2c_bus *i2c_bus, unsigned rate)
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{
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int ret;
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ret = reset_assert(&i2c_bus->reset_ctl);
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if (ret)
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return ret;
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ret = clk_enable(&i2c_bus->clk);
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if (ret)
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return ret;
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ret = clk_set_rate(&i2c_bus->clk, rate);
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if (IS_ERR_VALUE(ret))
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return ret;
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ret = reset_deassert(&i2c_bus->reset_ctl);
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if (ret)
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return ret;
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return 0;
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}
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static void i2c_init_controller(struct i2c_bus *i2c_bus)
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{
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if (!i2c_bus->speed)
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return;
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debug("%s: speed=%d\n", __func__, i2c_bus->speed);
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/*
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* Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
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* here, in section 23.3.1, but in fact we seem to need a factor of
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* 16 to get the right frequency.
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*/
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i2c_init_clock(i2c_bus, i2c_bus->speed * 2 * 8);
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if (i2c_bus->type == TYPE_114) {
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/*
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* T114 I2C went to a single clock source for standard/fast and
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* HS clock speeds. The new clock rate setting calculation is:
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* SCL = CLK_SOURCE.I2C /
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* (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) *
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* I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1).
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*
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* NOTE: We do this here, after the initial clock/pll start,
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* because if we read the clk_div reg before the controller
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* is running, we hang, and we need it for the new calc.
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*/
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int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16;
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unsigned rate = CLK_MULT_STD_FAST_MODE *
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(clk_div_stdfst_mode + 1) * i2c_bus->speed * 2;
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debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__,
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clk_div_stdfst_mode);
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i2c_init_clock(i2c_bus, rate);
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}
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/* Reset I2C controller. */
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i2c_reset_controller(i2c_bus);
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/* Configure I2C controller. */
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if (i2c_bus->type == TYPE_DVC) { /* only for DVC I2C */
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struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
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setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK);
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}
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#ifndef CONFIG_TEGRA186
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funcmux_select(i2c_bus->clk.id, i2c_bus->pinmux_config);
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#endif
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}
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static void send_packet_headers(
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struct i2c_bus *i2c_bus,
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struct i2c_trans_info *trans,
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u32 packet_id,
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bool end_with_repeated_start)
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{
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u32 data;
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/* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */
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data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT;
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data |= packet_id << PKT_HDR1_PKT_ID_SHIFT;
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data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT;
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writel(data, &i2c_bus->control->tx_fifo);
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debug("pkt header 1 sent (0x%x)\n", data);
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/* prepare header2 */
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data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT;
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writel(data, &i2c_bus->control->tx_fifo);
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debug("pkt header 2 sent (0x%x)\n", data);
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/* prepare IO specific header: configure the slave address */
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data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT;
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/* Enable Read if it is not a write transaction */
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if (!(trans->flags & I2C_IS_WRITE))
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data |= PKT_HDR3_READ_MODE_MASK;
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if (end_with_repeated_start)
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data |= PKT_HDR3_REPEAT_START_MASK;
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/* Write I2C specific header */
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writel(data, &i2c_bus->control->tx_fifo);
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debug("pkt header 3 sent (0x%x)\n", data);
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}
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static int wait_for_tx_fifo_empty(struct i2c_control *control)
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{
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u32 count;
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int timeout_us = I2C_TIMEOUT_USEC;
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while (timeout_us >= 0) {
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count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK)
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>> TX_FIFO_EMPTY_CNT_SHIFT;
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if (count == I2C_FIFO_DEPTH)
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return 1;
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udelay(10);
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timeout_us -= 10;
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}
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return 0;
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}
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static int wait_for_rx_fifo_notempty(struct i2c_control *control)
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{
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u32 count;
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int timeout_us = I2C_TIMEOUT_USEC;
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while (timeout_us >= 0) {
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count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK)
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>> TX_FIFO_FULL_CNT_SHIFT;
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if (count)
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return 1;
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udelay(10);
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timeout_us -= 10;
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}
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return 0;
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}
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static int wait_for_transfer_complete(struct i2c_control *control)
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{
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int int_status;
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int timeout_us = I2C_TIMEOUT_USEC;
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while (timeout_us >= 0) {
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int_status = readl(&control->int_status);
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if (int_status & I2C_INT_NO_ACK_MASK)
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return -int_status;
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if (int_status & I2C_INT_ARBITRATION_LOST_MASK)
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return -int_status;
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if (int_status & I2C_INT_XFER_COMPLETE_MASK)
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return 0;
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udelay(10);
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timeout_us -= 10;
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}
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return -1;
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}
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static int send_recv_packets(struct i2c_bus *i2c_bus,
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struct i2c_trans_info *trans)
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{
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struct i2c_control *control = i2c_bus->control;
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u32 int_status;
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u32 words;
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u8 *dptr;
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u32 local;
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uchar last_bytes;
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int error = 0;
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int is_write = trans->flags & I2C_IS_WRITE;
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/* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */
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int_status = readl(&control->int_status);
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writel(int_status, &control->int_status);
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send_packet_headers(i2c_bus, trans, 1,
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trans->flags & I2C_USE_REPEATED_START);
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words = DIV_ROUND_UP(trans->num_bytes, 4);
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last_bytes = trans->num_bytes & 3;
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dptr = trans->buf;
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while (words) {
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u32 *wptr = (u32 *)dptr;
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if (is_write) {
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/* deal with word alignment */
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if ((words == 1) && last_bytes) {
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local = 0;
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memcpy(&local, dptr, last_bytes);
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} else if ((unsigned long)dptr & 3) {
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memcpy(&local, dptr, sizeof(u32));
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} else {
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local = *wptr;
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}
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writel(local, &control->tx_fifo);
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debug("pkt data sent (0x%x)\n", local);
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if (!wait_for_tx_fifo_empty(control)) {
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error = -1;
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goto exit;
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}
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} else {
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if (!wait_for_rx_fifo_notempty(control)) {
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error = -1;
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goto exit;
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}
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/*
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* for the last word, we read into our local buffer,
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* in case that caller did not provide enough buffer.
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*/
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local = readl(&control->rx_fifo);
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if ((words == 1) && last_bytes)
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memcpy(dptr, (char *)&local, last_bytes);
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else if ((unsigned long)dptr & 3)
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memcpy(dptr, &local, sizeof(u32));
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else
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*wptr = local;
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debug("pkt data received (0x%x)\n", local);
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}
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words--;
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dptr += sizeof(u32);
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}
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if (wait_for_transfer_complete(control)) {
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error = -1;
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goto exit;
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}
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return 0;
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exit:
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/* error, reset the controller. */
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i2c_reset_controller(i2c_bus);
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return error;
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}
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static int tegra_i2c_write_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
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u32 len, bool end_with_repeated_start)
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{
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int error;
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struct i2c_trans_info trans_info;
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trans_info.address = addr;
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trans_info.buf = data;
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trans_info.flags = I2C_IS_WRITE;
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if (end_with_repeated_start)
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trans_info.flags |= I2C_USE_REPEATED_START;
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trans_info.num_bytes = len;
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trans_info.is_10bit_address = 0;
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error = send_recv_packets(i2c_bus, &trans_info);
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if (error)
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debug("tegra_i2c_write_data: Error (%d) !!!\n", error);
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return error;
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}
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static int tegra_i2c_read_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
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u32 len)
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{
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int error;
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struct i2c_trans_info trans_info;
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trans_info.address = addr | 1;
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trans_info.buf = data;
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trans_info.flags = 0;
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trans_info.num_bytes = len;
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trans_info.is_10bit_address = 0;
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error = send_recv_packets(i2c_bus, &trans_info);
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if (error)
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debug("tegra_i2c_read_data: Error (%d) !!!\n", error);
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return error;
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}
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static int tegra_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
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{
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struct i2c_bus *i2c_bus = dev_get_priv(dev);
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i2c_bus->speed = speed;
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i2c_init_controller(i2c_bus);
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return 0;
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}
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static int tegra_i2c_probe(struct udevice *dev)
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{
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struct i2c_bus *i2c_bus = dev_get_priv(dev);
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int ret;
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bool is_dvc;
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i2c_bus->id = dev_seq(dev);
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i2c_bus->type = dev_get_driver_data(dev);
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i2c_bus->regs = dev_read_addr_ptr(dev);
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if (!i2c_bus->regs) {
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debug("%s: Cannot get regs address\n", __func__);
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return -EINVAL;
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}
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ret = reset_get_by_name(dev, "i2c", &i2c_bus->reset_ctl);
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if (ret) {
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pr_err("reset_get_by_name() failed: %d\n", ret);
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return ret;
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}
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ret = clk_get_by_name(dev, "div-clk", &i2c_bus->clk);
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if (ret) {
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pr_err("clk_get_by_name() failed: %d\n", ret);
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return ret;
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}
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#ifndef CONFIG_TEGRA186
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/*
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* We don't have a binding for pinmux yet. Leave it out for now. So
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* far no one needs anything other than the default.
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*/
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i2c_bus->pinmux_config = FUNCMUX_DEFAULT;
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/*
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* We can't specify the pinmux config in the fdt, so I2C2 will not
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* work on Seaboard. It normally has no devices on it anyway.
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* You could add in this little hack if you need to use it.
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* The correct solution is a pinmux binding in the fdt.
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*
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* if (i2c_bus->clk.id == PERIPH_ID_I2C2)
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* i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
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*/
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#endif
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is_dvc = dev_get_driver_data(dev) == TYPE_DVC;
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if (is_dvc) {
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i2c_bus->control =
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&((struct dvc_ctlr *)i2c_bus->regs)->control;
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} else {
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i2c_bus->control = &i2c_bus->regs->control;
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}
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i2c_init_controller(i2c_bus);
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debug("%s: controller bus %d at %p, speed %d: ",
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is_dvc ? "dvc" : "i2c", dev_seq(dev), i2c_bus->regs,
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i2c_bus->speed);
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return 0;
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}
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/* i2c write version without the register address */
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static int i2c_write_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
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int len, bool end_with_repeated_start)
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{
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int rc;
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debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
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debug("write_data: ");
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/* use rc for counter */
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for (rc = 0; rc < len; ++rc)
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debug(" 0x%02x", buffer[rc]);
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debug("\n");
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/* Shift 7-bit address over for lower-level i2c functions */
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rc = tegra_i2c_write_data(i2c_bus, chip << 1, buffer, len,
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end_with_repeated_start);
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if (rc)
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debug("i2c_write_data(): rc=%d\n", rc);
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return rc;
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}
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/* i2c read version without the register address */
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static int i2c_read_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
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int len)
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{
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int rc;
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debug("inside i2c_read_data():\n");
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/* Shift 7-bit address over for lower-level i2c functions */
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rc = tegra_i2c_read_data(i2c_bus, chip << 1, buffer, len);
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if (rc) {
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debug("i2c_read_data(): rc=%d\n", rc);
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return rc;
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}
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debug("i2c_read_data: ");
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/* reuse rc for counter*/
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for (rc = 0; rc < len; ++rc)
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debug(" 0x%02x", buffer[rc]);
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debug("\n");
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return 0;
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}
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/* Probe to see if a chip is present. */
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static int tegra_i2c_probe_chip(struct udevice *bus, uint chip_addr,
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uint chip_flags)
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{
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struct i2c_bus *i2c_bus = dev_get_priv(bus);
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int rc;
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u8 reg;
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/* Shift 7-bit address over for lower-level i2c functions */
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rc = tegra_i2c_write_data(i2c_bus, chip_addr << 1, ®, sizeof(reg),
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false);
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return rc;
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}
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static int tegra_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
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int nmsgs)
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{
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struct i2c_bus *i2c_bus = dev_get_priv(bus);
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int ret;
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debug("i2c_xfer: %d messages\n", nmsgs);
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for (; nmsgs > 0; nmsgs--, msg++) {
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|
bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
|
|
|
|
debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
|
|
if (msg->flags & I2C_M_RD) {
|
|
ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
|
|
msg->len);
|
|
} else {
|
|
ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
|
|
msg->len, next_is_read);
|
|
}
|
|
if (ret) {
|
|
debug("i2c_write: error sending\n");
|
|
return -EREMOTEIO;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int tegra_i2c_get_dvc_bus(struct udevice **busp)
|
|
{
|
|
return uclass_first_device_drvdata(UCLASS_I2C, TYPE_DVC, busp);
|
|
}
|
|
|
|
static const struct dm_i2c_ops tegra_i2c_ops = {
|
|
.xfer = tegra_i2c_xfer,
|
|
.probe_chip = tegra_i2c_probe_chip,
|
|
.set_bus_speed = tegra_i2c_set_bus_speed,
|
|
};
|
|
|
|
static const struct udevice_id tegra_i2c_ids[] = {
|
|
{ .compatible = "nvidia,tegra114-i2c", .data = TYPE_114 },
|
|
{ .compatible = "nvidia,tegra124-i2c", .data = TYPE_114 },
|
|
{ .compatible = "nvidia,tegra20-i2c", .data = TYPE_STD },
|
|
{ .compatible = "nvidia,tegra20-i2c-dvc", .data = TYPE_DVC },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(i2c_tegra) = {
|
|
.name = "i2c_tegra",
|
|
.id = UCLASS_I2C,
|
|
.of_match = tegra_i2c_ids,
|
|
.probe = tegra_i2c_probe,
|
|
.priv_auto = sizeof(struct i2c_bus),
|
|
.ops = &tegra_i2c_ops,
|
|
};
|