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1353b25ec5
This functionality is part of the legacy I2C subsystem and is currently unused anywhere. Remove the remaining references. Signed-off-by: Tom Rini <trini@konsulko.com>
549 lines
13 KiB
C
549 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2000
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* Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
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*
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* (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2003 Pengutronix e.K.
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* Robert Schwebel <r.schwebel@pengutronix.de>
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*
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* (C) Copyright 2011 Marvell Inc.
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* Lei Wen <leiwen@marvell.com>
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*
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* Back ported to the 8xx platform (from the 8260 platform) by
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* Murray.Jensen@cmst.csiro.au, 27-Jan-01.
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*/
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#include <common.h>
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#include <dm.h>
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#include <i2c.h>
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#include <log.h>
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#include <asm/io.h>
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#include <linux/delay.h>
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#include "mv_i2c.h"
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/* All transfers are described by this data structure */
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struct mv_i2c_msg {
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u8 condition;
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u8 acknack;
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u8 direction;
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u8 data;
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};
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#ifdef CONFIG_ARMADA_3700
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/* Armada 3700 has no padding between the registers */
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struct mv_i2c {
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u32 ibmr;
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u32 idbr;
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u32 icr;
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u32 isr;
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u32 isar;
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};
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#else
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struct mv_i2c {
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u32 ibmr;
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u32 pad0;
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u32 idbr;
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u32 pad1;
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u32 icr;
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u32 pad2;
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u32 isr;
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u32 pad3;
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u32 isar;
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};
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#endif
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/*
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* Dummy implementation that can be overwritten by a board
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* specific function
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*/
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__weak void i2c_clk_enable(void)
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{
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}
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/*
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* i2c_reset: - reset the host controller
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*
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*/
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static void i2c_reset(struct mv_i2c *base)
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{
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u32 icr_mode;
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/* Save bus mode (standard or fast speed) for later use */
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icr_mode = readl(&base->icr) & ICR_MODE_MASK;
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writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
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writel(readl(&base->icr) | ICR_UR, &base->icr); /* reset the unit */
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udelay(100);
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writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
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i2c_clk_enable();
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writel(0x0, &base->isar); /* set our slave address */
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/* set control reg values */
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writel(I2C_ICR_INIT | icr_mode, &base->icr);
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writel(I2C_ISR_INIT, &base->isr); /* set clear interrupt bits */
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writel(readl(&base->icr) | ICR_IUE, &base->icr); /* enable unit */
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udelay(100);
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}
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/*
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* i2c_isr_set_cleared: - wait until certain bits of the I2C status register
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* are set and cleared
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*
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* @return: 1 in case of success, 0 means timeout (no match within 10 ms).
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*/
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static int i2c_isr_set_cleared(struct mv_i2c *base, unsigned long set_mask,
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unsigned long cleared_mask)
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{
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int timeout = 1000, isr;
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do {
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isr = readl(&base->isr);
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udelay(10);
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if (timeout-- < 0)
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return 0;
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} while (((isr & set_mask) != set_mask)
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|| ((isr & cleared_mask) != 0));
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return 1;
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}
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/*
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* i2c_transfer: - Transfer one byte over the i2c bus
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*
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* This function can tranfer a byte over the i2c bus in both directions.
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* It is used by the public API functions.
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*
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* @return: 0: transfer successful
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* -1: message is empty
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* -2: transmit timeout
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* -3: ACK missing
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* -4: receive timeout
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* -5: illegal parameters
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* -6: bus is busy and couldn't be aquired
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*/
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static int i2c_transfer(struct mv_i2c *base, struct mv_i2c_msg *msg)
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{
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int ret;
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if (!msg)
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goto transfer_error_msg_empty;
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switch (msg->direction) {
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case I2C_WRITE:
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/* check if bus is not busy */
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if (!i2c_isr_set_cleared(base, 0, ISR_IBB))
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goto transfer_error_bus_busy;
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/* start transmission */
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writel(readl(&base->icr) & ~ICR_START, &base->icr);
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writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
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writel(msg->data, &base->idbr);
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if (msg->condition == I2C_COND_START)
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writel(readl(&base->icr) | ICR_START, &base->icr);
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if (msg->condition == I2C_COND_STOP)
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writel(readl(&base->icr) | ICR_STOP, &base->icr);
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if (msg->acknack == I2C_ACKNAK_SENDNAK)
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writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
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if (msg->acknack == I2C_ACKNAK_SENDACK)
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writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
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writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
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writel(readl(&base->icr) | ICR_TB, &base->icr);
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/* transmit register empty? */
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if (!i2c_isr_set_cleared(base, ISR_ITE, 0))
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goto transfer_error_transmit_timeout;
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/* clear 'transmit empty' state */
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writel(readl(&base->isr) | ISR_ITE, &base->isr);
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/* wait for ACK from slave */
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if (msg->acknack == I2C_ACKNAK_WAITACK)
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if (!i2c_isr_set_cleared(base, 0, ISR_ACKNAK))
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goto transfer_error_ack_missing;
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break;
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case I2C_READ:
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/* check if bus is not busy */
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if (!i2c_isr_set_cleared(base, 0, ISR_IBB))
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goto transfer_error_bus_busy;
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/* start receive */
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writel(readl(&base->icr) & ~ICR_START, &base->icr);
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writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
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if (msg->condition == I2C_COND_START)
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writel(readl(&base->icr) | ICR_START, &base->icr);
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if (msg->condition == I2C_COND_STOP)
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writel(readl(&base->icr) | ICR_STOP, &base->icr);
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if (msg->acknack == I2C_ACKNAK_SENDNAK)
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writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
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if (msg->acknack == I2C_ACKNAK_SENDACK)
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writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
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writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
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writel(readl(&base->icr) | ICR_TB, &base->icr);
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/* receive register full? */
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if (!i2c_isr_set_cleared(base, ISR_IRF, 0))
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goto transfer_error_receive_timeout;
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msg->data = readl(&base->idbr);
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/* clear 'receive empty' state */
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writel(readl(&base->isr) | ISR_IRF, &base->isr);
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break;
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default:
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goto transfer_error_illegal_param;
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}
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return 0;
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transfer_error_msg_empty:
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debug("i2c_transfer: error: 'msg' is empty\n");
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ret = -1;
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goto i2c_transfer_finish;
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transfer_error_transmit_timeout:
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debug("i2c_transfer: error: transmit timeout\n");
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ret = -2;
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goto i2c_transfer_finish;
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transfer_error_ack_missing:
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debug("i2c_transfer: error: ACK missing\n");
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ret = -3;
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goto i2c_transfer_finish;
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transfer_error_receive_timeout:
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debug("i2c_transfer: error: receive timeout\n");
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ret = -4;
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goto i2c_transfer_finish;
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transfer_error_illegal_param:
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debug("i2c_transfer: error: illegal parameters\n");
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ret = -5;
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goto i2c_transfer_finish;
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transfer_error_bus_busy:
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debug("i2c_transfer: error: bus is busy\n");
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ret = -6;
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goto i2c_transfer_finish;
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i2c_transfer_finish:
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debug("i2c_transfer: ISR: 0x%04x\n", readl(&base->isr));
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i2c_reset(base);
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return ret;
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}
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static int __i2c_read(struct mv_i2c *base, uchar chip, u8 *addr, int alen,
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uchar *buffer, int len)
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{
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struct mv_i2c_msg msg;
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debug("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
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"len=0x%02x)\n", chip, *addr, alen, len);
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if (len == 0) {
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printf("reading zero byte is invalid\n");
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return -EINVAL;
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}
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i2c_reset(base);
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/* dummy chip address write */
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debug("i2c_read: dummy chip address write\n");
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msg.condition = I2C_COND_START;
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msg.acknack = I2C_ACKNAK_WAITACK;
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msg.direction = I2C_WRITE;
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msg.data = (chip << 1);
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msg.data &= 0xFE;
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if (i2c_transfer(base, &msg))
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return -1;
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/*
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* send memory address bytes;
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* alen defines how much bytes we have to send.
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*/
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while (--alen >= 0) {
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debug("i2c_read: send address byte %02x (alen=%d)\n",
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*addr, alen);
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msg.condition = I2C_COND_NORMAL;
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msg.acknack = I2C_ACKNAK_WAITACK;
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msg.direction = I2C_WRITE;
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msg.data = addr[alen];
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if (i2c_transfer(base, &msg))
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return -1;
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}
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/* start read sequence */
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debug("i2c_read: start read sequence\n");
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msg.condition = I2C_COND_START;
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msg.acknack = I2C_ACKNAK_WAITACK;
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msg.direction = I2C_WRITE;
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msg.data = (chip << 1);
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msg.data |= 0x01;
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if (i2c_transfer(base, &msg))
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return -1;
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/* read bytes; send NACK at last byte */
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while (len--) {
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if (len == 0) {
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msg.condition = I2C_COND_STOP;
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msg.acknack = I2C_ACKNAK_SENDNAK;
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} else {
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msg.condition = I2C_COND_NORMAL;
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msg.acknack = I2C_ACKNAK_SENDACK;
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}
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msg.direction = I2C_READ;
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msg.data = 0x00;
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if (i2c_transfer(base, &msg))
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return -1;
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*buffer = msg.data;
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debug("i2c_read: reading byte (%p)=0x%02x\n",
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buffer, *buffer);
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buffer++;
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}
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i2c_reset(base);
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return 0;
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}
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static int __i2c_write(struct mv_i2c *base, uchar chip, u8 *addr, int alen,
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uchar *buffer, int len)
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{
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struct mv_i2c_msg msg;
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debug("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
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"len=0x%02x)\n", chip, *addr, alen, len);
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i2c_reset(base);
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/* chip address write */
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debug("i2c_write: chip address write\n");
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msg.condition = I2C_COND_START;
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msg.acknack = I2C_ACKNAK_WAITACK;
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msg.direction = I2C_WRITE;
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msg.data = (chip << 1);
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msg.data &= 0xFE;
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if (i2c_transfer(base, &msg))
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return -1;
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/*
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* send memory address bytes;
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* alen defines how much bytes we have to send.
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*/
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while (--alen >= 0) {
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debug("i2c_read: send address byte %02x (alen=%d)\n",
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*addr, alen);
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msg.condition = I2C_COND_NORMAL;
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msg.acknack = I2C_ACKNAK_WAITACK;
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msg.direction = I2C_WRITE;
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msg.data = addr[alen];
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if (i2c_transfer(base, &msg))
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return -1;
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}
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/* write bytes; send NACK at last byte */
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while (len--) {
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debug("i2c_write: writing byte (%p)=0x%02x\n",
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buffer, *buffer);
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if (len == 0)
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msg.condition = I2C_COND_STOP;
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else
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msg.condition = I2C_COND_NORMAL;
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msg.acknack = I2C_ACKNAK_WAITACK;
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msg.direction = I2C_WRITE;
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msg.data = *(buffer++);
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if (i2c_transfer(base, &msg))
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return -1;
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}
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i2c_reset(base);
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return 0;
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}
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#if !CONFIG_IS_ENABLED(DM_I2C)
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static struct mv_i2c *base_glob;
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/* API Functions */
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void i2c_init(int speed, int slaveaddr)
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{
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u32 val;
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base_glob = (struct mv_i2c *)CONFIG_MV_I2C_REG;
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if (speed > I2C_SPEED_STANDARD_RATE)
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val = ICR_FM;
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else
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val = ICR_SM;
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clrsetbits_le32(&base_glob->icr, ICR_MODE_MASK, val);
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}
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static int __i2c_probe_chip(struct mv_i2c *base, uchar chip)
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{
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struct mv_i2c_msg msg;
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i2c_reset(base);
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msg.condition = I2C_COND_START;
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msg.acknack = I2C_ACKNAK_WAITACK;
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msg.direction = I2C_WRITE;
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msg.data = (chip << 1) + 1;
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if (i2c_transfer(base, &msg))
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return -1;
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msg.condition = I2C_COND_STOP;
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msg.acknack = I2C_ACKNAK_SENDNAK;
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msg.direction = I2C_READ;
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msg.data = 0x00;
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if (i2c_transfer(base, &msg))
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return -1;
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return 0;
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}
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/*
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* i2c_probe: - Test if a chip answers for a given i2c address
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*
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* @chip: address of the chip which is searched for
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* @return: 0 if a chip was found, -1 otherwhise
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*/
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int i2c_probe(uchar chip)
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{
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return __i2c_probe_chip(base_glob, chip);
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}
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/*
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* i2c_read: - Read multiple bytes from an i2c device
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*
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* The higher level routines take into account that this function is only
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* called with len < page length of the device (see configuration file)
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*
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* @chip: address of the chip which is to be read
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* @addr: i2c data address within the chip
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* @alen: length of the i2c data address (1..2 bytes)
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* @buffer: where to write the data
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* @len: how much byte do we want to read
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* @return: 0 in case of success
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*/
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int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
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{
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u8 addr_bytes[4];
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addr_bytes[0] = (addr >> 0) & 0xFF;
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addr_bytes[1] = (addr >> 8) & 0xFF;
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addr_bytes[2] = (addr >> 16) & 0xFF;
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addr_bytes[3] = (addr >> 24) & 0xFF;
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return __i2c_read(base_glob, chip, addr_bytes, alen, buffer, len);
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}
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/*
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* i2c_write: - Write multiple bytes to an i2c device
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*
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* The higher level routines take into account that this function is only
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* called with len < page length of the device (see configuration file)
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*
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* @chip: address of the chip which is to be written
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* @addr: i2c data address within the chip
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* @alen: length of the i2c data address (1..2 bytes)
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* @buffer: where to find the data to be written
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* @len: how much byte do we want to read
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* @return: 0 in case of success
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*/
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int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
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{
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u8 addr_bytes[4];
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addr_bytes[0] = (addr >> 0) & 0xFF;
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addr_bytes[1] = (addr >> 8) & 0xFF;
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addr_bytes[2] = (addr >> 16) & 0xFF;
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addr_bytes[3] = (addr >> 24) & 0xFF;
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return __i2c_write(base_glob, chip, addr_bytes, alen, buffer, len);
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}
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#else /* CONFIG_DM_I2C */
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struct mv_i2c_priv {
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struct mv_i2c *base;
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};
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static int mv_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
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{
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struct mv_i2c_priv *i2c = dev_get_priv(bus);
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struct i2c_msg *dmsg, *omsg, dummy;
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memset(&dummy, 0, sizeof(struct i2c_msg));
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/*
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* We expect either two messages (one with an offset and one with the
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* actual data) or one message (just data or offset/data combined)
|
|
*/
|
|
if (nmsgs > 2 || nmsgs == 0) {
|
|
debug("%s: Only one or two messages are supported.", __func__);
|
|
return -1;
|
|
}
|
|
|
|
omsg = nmsgs == 1 ? &dummy : msg;
|
|
dmsg = nmsgs == 1 ? msg : msg + 1;
|
|
|
|
if (dmsg->flags & I2C_M_RD)
|
|
return __i2c_read(i2c->base, dmsg->addr, omsg->buf,
|
|
omsg->len, dmsg->buf, dmsg->len);
|
|
else
|
|
return __i2c_write(i2c->base, dmsg->addr, omsg->buf,
|
|
omsg->len, dmsg->buf, dmsg->len);
|
|
}
|
|
|
|
static int mv_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
|
|
{
|
|
struct mv_i2c_priv *priv = dev_get_priv(bus);
|
|
u32 val;
|
|
|
|
if (speed > I2C_SPEED_STANDARD_RATE)
|
|
val = ICR_FM;
|
|
else
|
|
val = ICR_SM;
|
|
clrsetbits_le32(&priv->base->icr, ICR_MODE_MASK, val);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mv_i2c_probe(struct udevice *bus)
|
|
{
|
|
struct mv_i2c_priv *priv = dev_get_priv(bus);
|
|
|
|
priv->base = dev_read_addr_ptr(bus);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dm_i2c_ops mv_i2c_ops = {
|
|
.xfer = mv_i2c_xfer,
|
|
.set_bus_speed = mv_i2c_set_bus_speed,
|
|
};
|
|
|
|
static const struct udevice_id mv_i2c_ids[] = {
|
|
{ .compatible = "marvell,armada-3700-i2c" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(i2c_mv) = {
|
|
.name = "i2c_mv",
|
|
.id = UCLASS_I2C,
|
|
.of_match = mv_i2c_ids,
|
|
.probe = mv_i2c_probe,
|
|
.priv_auto = sizeof(struct mv_i2c_priv),
|
|
.ops = &mv_i2c_ops,
|
|
};
|
|
#endif /* CONFIG_DM_I2C */
|