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9ad71f6340
This patch adds support for MediaTek I2C interface Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
822 lines
21 KiB
C
822 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022 MediaTek Inc. All Rights Reserved.
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*
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* Author: Mingming Lee <Mingming.Lee@mediatek.com>
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*
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* MediaTek I2C Interface driver
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*/
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#include <clk.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <i2c.h>
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#include <log.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#define I2C_RS_TRANSFER BIT(4)
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#define I2C_HS_NACKERR BIT(2)
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#define I2C_ACKERR BIT(1)
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#define I2C_TRANSAC_COMP BIT(0)
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#define I2C_TRANSAC_START BIT(0)
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#define I2C_RS_MUL_CNFG BIT(15)
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#define I2C_RS_MUL_TRIG BIT(14)
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#define I2C_DCM_DISABLE 0x0000
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#define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
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#define I2C_IO_CONFIG_PUSH_PULL 0x0000
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#define I2C_SOFT_RST 0x0001
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#define I2C_FIFO_ADDR_CLR 0x0001
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#define I2C_DELAY_LEN 0x0002
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#define I2C_ST_START_CON 0x8001
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#define I2C_FS_START_CON 0x1800
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#define I2C_TIME_CLR_VALUE 0x0000
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#define I2C_TIME_DEFAULT_VALUE 0x0003
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#define I2C_WRRD_TRANAC_VALUE 0x0002
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#define I2C_RD_TRANAC_VALUE 0x0001
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#define I2C_DMA_CON_TX 0x0000
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#define I2C_DMA_CON_RX 0x0001
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#define I2C_DMA_START_EN 0x0001
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#define I2C_DMA_INT_FLAG_NONE 0x0000
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#define I2C_DMA_CLR_FLAG 0x0000
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#define I2C_DMA_TX_RX 0x0000
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#define I2C_DMA_HARD_RST 0x0002
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#define MAX_ST_MODE_SPEED 100000
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#define MAX_FS_MODE_SPEED 400000
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#define MAX_HS_MODE_SPEED 3400000
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#define MAX_SAMPLE_CNT_DIV 8
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#define MAX_STEP_CNT_DIV 64
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#define MAX_HS_STEP_CNT_DIV 8
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#define I2C_DEFAULT_CLK_DIV 4
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#define MAX_I2C_ADDR 0x7f
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#define MAX_I2C_LEN 0xff
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#define TRANS_ADDR_ONLY BIT(8)
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#define TRANSFER_TIMEOUT 50000 /* us */
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#define I2C_FIFO_STAT1_MASK 0x001f
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#define TIMING_SAMPLE_OFFSET 8
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#define HS_SAMPLE_OFFSET 12
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#define HS_STEP_OFFSET 8
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#define I2C_CONTROL_WRAPPER BIT(0)
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#define I2C_CONTROL_RS BIT(1)
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#define I2C_CONTROL_DMA_EN BIT(2)
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#define I2C_CONTROL_CLK_EXT_EN BIT(3)
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#define I2C_CONTROL_DIR_CHANGE BIT(4)
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#define I2C_CONTROL_ACKERR_DET_EN BIT(5)
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#define I2C_CONTROL_TRANSFER_LEN_CHANGE BIT(6)
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#define I2C_CONTROL_DMAACK BIT(8)
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#define I2C_CONTROL_ASYNC BIT(9)
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#define I2C_MASTER_WR BIT(0)
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#define I2C_MASTER_RD BIT(1)
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#define I2C_MASTER_WRRD (I2C_MASTER_WR | I2C_MASTER_RD)
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enum I2C_REGS_OFFSET {
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REG_PORT,
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REG_SLAVE_ADDR,
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REG_INTR_MASK,
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REG_INTR_STAT,
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REG_CONTROL,
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REG_TRANSFER_LEN,
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REG_TRANSAC_LEN,
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REG_DELAY_LEN,
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REG_TIMING,
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REG_START,
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REG_EXT_CONF,
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REG_FIFO_STAT1,
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REG_LTIMING,
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REG_FIFO_STAT,
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REG_FIFO_THRESH,
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REG_FIFO_ADDR_CLR,
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REG_IO_CONFIG,
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REG_RSV_DEBUG,
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REG_HS,
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REG_SOFTRESET,
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REG_DCM_EN,
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REG_PATH_DIR,
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REG_DEBUGSTAT,
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REG_DEBUGCTRL,
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REG_TRANSFER_LEN_AUX,
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REG_CLOCK_DIV,
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REG_SCL_HL_RATIO,
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REG_SCL_HS_HL_RATIO,
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REG_SCL_MIS_COMP_POINT,
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REG_STA_STOP_AC_TIME,
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REG_HS_STA_STOP_AC_TIME,
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REG_DATA_TIME,
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};
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enum DMA_REGS_OFFSET {
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REG_INT_FLAG = 0x0,
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REG_INT_EN = 0x04,
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REG_EN = 0x08,
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REG_RST = 0x0c,
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REG_CON = 0x18,
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REG_TX_MEM_ADDR = 0x1c,
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REG_RX_MEM_ADDR = 0x20,
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REG_TX_LEN = 0x24,
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REG_RX_LEN = 0x28,
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};
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static const uint mt_i2c_regs_v1[] = {
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[REG_PORT] = 0x0,
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[REG_SLAVE_ADDR] = 0x4,
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[REG_INTR_MASK] = 0x8,
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[REG_INTR_STAT] = 0xc,
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[REG_CONTROL] = 0x10,
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[REG_TRANSFER_LEN] = 0x14,
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[REG_TRANSAC_LEN] = 0x18,
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[REG_DELAY_LEN] = 0x1c,
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[REG_TIMING] = 0x20,
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[REG_START] = 0x24,
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[REG_EXT_CONF] = 0x28,
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[REG_FIFO_STAT1] = 0x2c,
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[REG_FIFO_STAT] = 0x30,
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[REG_FIFO_THRESH] = 0x34,
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[REG_FIFO_ADDR_CLR] = 0x38,
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[REG_IO_CONFIG] = 0x40,
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[REG_RSV_DEBUG] = 0x44,
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[REG_HS] = 0x48,
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[REG_SOFTRESET] = 0x50,
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[REG_SOFTRESET] = 0x50,
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[REG_DCM_EN] = 0x54,
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[REG_DEBUGSTAT] = 0x64,
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[REG_DEBUGCTRL] = 0x68,
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[REG_TRANSFER_LEN_AUX] = 0x6c,
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[REG_CLOCK_DIV] = 0x70,
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[REG_SCL_HL_RATIO] = 0x74,
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[REG_SCL_HS_HL_RATIO] = 0x78,
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[REG_SCL_MIS_COMP_POINT] = 0x7c,
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[REG_STA_STOP_AC_TIME] = 0x80,
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[REG_HS_STA_STOP_AC_TIME] = 0x84,
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[REG_DATA_TIME] = 0x88,
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};
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static const uint mt_i2c_regs_v2[] = {
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[REG_PORT] = 0x0,
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[REG_SLAVE_ADDR] = 0x4,
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[REG_INTR_MASK] = 0x8,
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[REG_INTR_STAT] = 0xc,
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[REG_CONTROL] = 0x10,
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[REG_TRANSFER_LEN] = 0x14,
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[REG_TRANSAC_LEN] = 0x18,
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[REG_DELAY_LEN] = 0x1c,
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[REG_TIMING] = 0x20,
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[REG_START] = 0x24,
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[REG_EXT_CONF] = 0x28,
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[REG_LTIMING] = 0x2c,
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[REG_HS] = 0x30,
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[REG_IO_CONFIG] = 0x34,
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[REG_FIFO_ADDR_CLR] = 0x38,
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[REG_TRANSFER_LEN_AUX] = 0x44,
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[REG_CLOCK_DIV] = 0x48,
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[REG_SOFTRESET] = 0x50,
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[REG_DEBUGSTAT] = 0xe0,
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[REG_DEBUGCTRL] = 0xe8,
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[REG_FIFO_STAT] = 0xf4,
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[REG_FIFO_THRESH] = 0xf8,
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[REG_DCM_EN] = 0xf88,
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};
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struct mtk_i2c_soc_data {
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const uint *regs;
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uint dma_sync: 1;
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};
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struct mtk_i2c_priv {
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/* set in i2c probe */
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void __iomem *base; /* i2c base addr */
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void __iomem *pdmabase; /* dma base address*/
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struct clk clk_main; /* main clock for i2c bus */
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struct clk clk_dma; /* DMA clock for i2c via DMA */
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const struct mtk_i2c_soc_data *soc_data; /* Compatible data for different IC */
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int op; /* operation mode */
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bool zero_len; /* Only transfer slave address, no data */
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bool pushpull; /* push pull mode or open drain mode */
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bool filter_msg; /* filter msg error log */
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bool auto_restart; /* restart mode */
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bool ignore_restart_irq; /* ignore restart IRQ */
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uint speed; /* i2c speed, unit: hz */
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};
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static inline void i2c_writel(struct mtk_i2c_priv *priv, uint reg, uint value)
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{
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u32 offset = priv->soc_data->regs[reg];
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writel(value, priv->base + offset);
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}
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static inline uint i2c_readl(struct mtk_i2c_priv *priv, uint offset)
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{
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return readl(priv->base + priv->soc_data->regs[offset]);
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}
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static int mtk_i2c_clk_enable(struct mtk_i2c_priv *priv)
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{
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int ret;
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ret = clk_enable(&priv->clk_main);
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if (ret)
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return log_msg_ret("enable clk_main", ret);
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ret = clk_enable(&priv->clk_dma);
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if (ret)
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return log_msg_ret("enable clk_dma", ret);
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return 0;
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}
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static int mtk_i2c_clk_disable(struct mtk_i2c_priv *priv)
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{
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int ret;
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ret = clk_disable(&priv->clk_dma);
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if (ret)
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return log_msg_ret("disable clk_dma", ret);
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ret = clk_disable(&priv->clk_main);
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if (ret)
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return log_msg_ret("disable clk_main", ret);
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return 0;
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}
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static void mtk_i2c_init_hw(struct mtk_i2c_priv *priv)
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{
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uint control_reg;
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writel(I2C_DMA_HARD_RST, priv->pdmabase + REG_RST);
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writel(I2C_DMA_CLR_FLAG, priv->pdmabase + REG_RST);
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i2c_writel(priv, REG_SOFTRESET, I2C_SOFT_RST);
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/* set ioconfig */
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if (priv->pushpull)
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i2c_writel(priv, REG_IO_CONFIG, I2C_IO_CONFIG_PUSH_PULL);
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else
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i2c_writel(priv, REG_IO_CONFIG, I2C_IO_CONFIG_OPEN_DRAIN);
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i2c_writel(priv, REG_DCM_EN, I2C_DCM_DISABLE);
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control_reg = I2C_CONTROL_ACKERR_DET_EN | I2C_CONTROL_CLK_EXT_EN;
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if (priv->soc_data->dma_sync)
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control_reg |= I2C_CONTROL_DMAACK | I2C_CONTROL_ASYNC;
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i2c_writel(priv, REG_CONTROL, control_reg);
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i2c_writel(priv, REG_DELAY_LEN, I2C_DELAY_LEN);
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}
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/*
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* Calculate i2c port speed
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*
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* Hardware design:
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* i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
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* clock_div: fixed in hardware, but may be various in different SoCs
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*
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* The calculation want to pick the highest bus frequency that is still
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* less than or equal to target_speed. The calculation try to get
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* sample_cnt and step_cn
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* @param[in]
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* clk_src: i2c clock source
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* @param[out]
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* timing_step_cnt: step cnt calculate result
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* @param[out]
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* timing_sample_cnt: sample cnt calculate result
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* @return
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* 0, set speed successfully.
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* -EINVAL, Unsupported speed.
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*/
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static int mtk_i2c_calculate_speed(uint clk_src,
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uint target_speed,
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uint *timing_step_cnt,
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uint *timing_sample_cnt)
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{
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uint base_sample_cnt = MAX_SAMPLE_CNT_DIV;
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uint base_step_cnt;
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uint max_step_cnt;
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uint sample_cnt;
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uint step_cnt;
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uint opt_div;
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uint best_mul;
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uint cnt_mul;
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if (target_speed > MAX_HS_MODE_SPEED)
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target_speed = MAX_HS_MODE_SPEED;
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if (target_speed > MAX_FS_MODE_SPEED)
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max_step_cnt = MAX_HS_STEP_CNT_DIV;
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else
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max_step_cnt = MAX_STEP_CNT_DIV;
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base_step_cnt = max_step_cnt;
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/* Find the best combination */
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opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
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best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
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/*
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* Search for the best pair (sample_cnt, step_cnt) with
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* 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
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* 0 < step_cnt < max_step_cnt
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* sample_cnt * step_cnt >= opt_div
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* optimizing for sample_cnt * step_cnt being minimal
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*/
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for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
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step_cnt = DIV_ROUND_UP(opt_div, sample_cnt);
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cnt_mul = step_cnt * sample_cnt;
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if (step_cnt > max_step_cnt)
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continue;
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if (cnt_mul < best_mul) {
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best_mul = cnt_mul;
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base_sample_cnt = sample_cnt;
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base_step_cnt = step_cnt;
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if (best_mul == opt_div)
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break;
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}
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}
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sample_cnt = base_sample_cnt;
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step_cnt = base_step_cnt;
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if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) {
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/*
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* In this case, hardware can't support such
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* low i2c_bus_freq
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*/
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debug("Unsupported speed(%uhz)\n", target_speed);
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return log_msg_ret("calculate speed", -EINVAL);
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}
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*timing_step_cnt = step_cnt - 1;
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*timing_sample_cnt = sample_cnt - 1;
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return 0;
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}
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/*
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* mtk_i2c_set_speed
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*
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* @par Description
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* Calculate i2c speed and write sample_cnt, step_cnt to TIMING register.
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* @param[in]
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* dev: udevice pointer, struct udevice contains i2c source clock,
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* clock divide and speed.
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* @return
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* 0, set speed successfully.\n
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* error code from mtk_i2c_calculate_speed().
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*/
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static int mtk_i2c_set_speed(struct udevice *dev, uint speed)
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{
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struct mtk_i2c_priv *priv = dev_get_priv(dev);
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uint high_speed_reg;
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uint sample_cnt;
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uint timing_reg;
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uint step_cnt;
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uint clk_src;
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int ret = 0;
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priv->speed = speed;
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if (mtk_i2c_clk_enable(priv))
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return log_msg_ret("set_speed enable clk", -1);
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clk_src = clk_get_rate(&priv->clk_main) / I2C_DEFAULT_CLK_DIV;
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i2c_writel(priv, REG_CLOCK_DIV, (I2C_DEFAULT_CLK_DIV - 1));
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if (priv->speed > MAX_FS_MODE_SPEED) {
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/* Set master code speed register */
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ret = mtk_i2c_calculate_speed(clk_src, MAX_FS_MODE_SPEED,
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&step_cnt, &sample_cnt);
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if (ret < 0)
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goto exit;
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timing_reg = (sample_cnt << TIMING_SAMPLE_OFFSET) | step_cnt;
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i2c_writel(priv, REG_TIMING, timing_reg);
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/* Set the high speed mode register */
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ret = mtk_i2c_calculate_speed(clk_src, priv->speed,
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&step_cnt, &sample_cnt);
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if (ret < 0)
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goto exit;
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high_speed_reg = I2C_TIME_DEFAULT_VALUE |
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(sample_cnt << HS_SAMPLE_OFFSET) |
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(step_cnt << HS_STEP_OFFSET);
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i2c_writel(priv, REG_HS, high_speed_reg);
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} else {
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ret = mtk_i2c_calculate_speed(clk_src, priv->speed,
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&step_cnt, &sample_cnt);
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if (ret < 0)
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goto exit;
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timing_reg = (sample_cnt << TIMING_SAMPLE_OFFSET) | step_cnt;
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/* Disable the high speed transaction */
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high_speed_reg = I2C_TIME_CLR_VALUE;
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i2c_writel(priv, REG_TIMING, timing_reg);
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i2c_writel(priv, REG_HS, high_speed_reg);
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}
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exit:
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if (mtk_i2c_clk_disable(priv))
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return log_msg_ret("set_speed disable clk", -1);
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return ret;
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}
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/*
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* mtk_i2c_do_transfer
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*
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* @par Description
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* Configure i2c register and trigger transfer.
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* @param[in]
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* priv: mtk_i2cmtk_i2c_priv pointer, struct mtk_i2c_priv contains register base\n
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* address, operation mode, interrupt status and i2c driver data.
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* @param[in]
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* msgs: i2c_msg pointer, struct i2c_msg contains slave\n
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* address, operation mode, msg length and data buffer.
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* @param[in]
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* num: i2c_msg number.
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* @param[in]
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* left_num: left i2c_msg number.
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* @return
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* 0, i2c transfer successfully.\n
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* -ETIMEDOUT, i2c transfer timeout.\n
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* -EREMOTEIO, i2c transfer ack error.
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*/
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static int mtk_i2c_do_transfer(struct mtk_i2c_priv *priv,
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struct i2c_msg *msgs,
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int num, int left_num)
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{
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struct i2c_msg *msg_rx = NULL;
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uint restart_flag = 0;
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uint trans_error = 0;
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uint irq_stat = 0;
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uint tmo_poll = 0;
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uint control_reg;
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bool tmo = false;
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uint start_reg;
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uint addr_reg;
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int ret = 0;
|
|
|
|
if (priv->auto_restart)
|
|
restart_flag = I2C_RS_TRANSFER;
|
|
|
|
control_reg = i2c_readl(priv, REG_CONTROL) &
|
|
~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
|
|
|
|
if (priv->speed > MAX_FS_MODE_SPEED || num > 1)
|
|
control_reg |= I2C_CONTROL_RS;
|
|
|
|
if (priv->op == I2C_MASTER_WRRD)
|
|
control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
|
|
|
|
control_reg |= I2C_CONTROL_DMA_EN;
|
|
i2c_writel(priv, REG_CONTROL, control_reg);
|
|
|
|
/* set start condition */
|
|
if (priv->speed <= MAX_ST_MODE_SPEED)
|
|
i2c_writel(priv, REG_EXT_CONF, I2C_ST_START_CON);
|
|
else
|
|
i2c_writel(priv, REG_EXT_CONF, I2C_FS_START_CON);
|
|
|
|
addr_reg = msgs->addr << 1;
|
|
if (priv->op == I2C_MASTER_RD)
|
|
addr_reg |= I2C_M_RD;
|
|
if (priv->zero_len)
|
|
i2c_writel(priv, REG_SLAVE_ADDR, addr_reg | TRANS_ADDR_ONLY);
|
|
else
|
|
i2c_writel(priv, REG_SLAVE_ADDR, addr_reg);
|
|
|
|
/* clear interrupt status */
|
|
i2c_writel(priv, REG_INTR_STAT, restart_flag | I2C_HS_NACKERR |
|
|
I2C_ACKERR | I2C_TRANSAC_COMP);
|
|
i2c_writel(priv, REG_FIFO_ADDR_CLR, I2C_FIFO_ADDR_CLR);
|
|
|
|
/* enable interrupt */
|
|
i2c_writel(priv, REG_INTR_MASK, restart_flag | I2C_HS_NACKERR |
|
|
I2C_ACKERR | I2C_TRANSAC_COMP);
|
|
|
|
/* set transfer and transaction len */
|
|
if (priv->op == I2C_MASTER_WRRD) {
|
|
i2c_writel(priv, REG_TRANSFER_LEN, msgs->len);
|
|
i2c_writel(priv, REG_TRANSFER_LEN_AUX, (msgs + 1)->len);
|
|
i2c_writel(priv, REG_TRANSAC_LEN, I2C_WRRD_TRANAC_VALUE);
|
|
} else {
|
|
i2c_writel(priv, REG_TRANSFER_LEN, msgs->len);
|
|
i2c_writel(priv, REG_TRANSAC_LEN, num);
|
|
}
|
|
|
|
/* Clear DMA interrupt flag */
|
|
writel(I2C_DMA_INT_FLAG_NONE, priv->pdmabase + REG_INT_FLAG);
|
|
|
|
/* Flush cache for first msg */
|
|
flush_cache((ulong)msgs->buf, msgs->len);
|
|
|
|
/*
|
|
* prepare buffer data to start transfer
|
|
* three cases here: read, write, write then read
|
|
*/
|
|
if (priv->op & I2C_MASTER_WR) {
|
|
/* Set DMA direction TX (w/ or w/o RX) */
|
|
writel(I2C_DMA_CON_TX, priv->pdmabase + REG_CON);
|
|
|
|
/* Write the tx buffer address to dma register */
|
|
writel((ulong)msgs->buf, priv->pdmabase + REG_TX_MEM_ADDR);
|
|
/* Write the tx length to dma register */
|
|
writel(msgs->len, priv->pdmabase + REG_TX_LEN);
|
|
|
|
if (priv->op & I2C_MASTER_RD) {
|
|
/* write then read */
|
|
msg_rx = msgs + 1;
|
|
|
|
/* Flush cache for second msg */
|
|
flush_cache((ulong)msg_rx->buf, msg_rx->len);
|
|
}
|
|
}
|
|
|
|
if (priv->op & I2C_MASTER_RD) {
|
|
if (!msg_rx) {
|
|
/* Set DMA direction RX */
|
|
writel(I2C_DMA_CON_RX, priv->pdmabase + REG_CON);
|
|
|
|
msg_rx = msgs;
|
|
}
|
|
|
|
/* Write the rx buffer address to dma register */
|
|
writel((ulong)msg_rx->buf, priv->pdmabase + REG_RX_MEM_ADDR);
|
|
/* Write the rx length to dma register */
|
|
writel(msg_rx->len, priv->pdmabase + REG_RX_LEN);
|
|
}
|
|
|
|
writel(I2C_DMA_START_EN, priv->pdmabase + REG_EN);
|
|
|
|
if (!priv->auto_restart) {
|
|
start_reg = I2C_TRANSAC_START;
|
|
} else {
|
|
start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG;
|
|
if (left_num >= 1)
|
|
start_reg |= I2C_RS_MUL_CNFG;
|
|
}
|
|
i2c_writel(priv, REG_START, start_reg);
|
|
|
|
for (;;) {
|
|
irq_stat = i2c_readl(priv, REG_INTR_STAT);
|
|
|
|
/* ignore the first restart irq after the master code */
|
|
if (priv->ignore_restart_irq && (irq_stat & restart_flag)) {
|
|
priv->ignore_restart_irq = false;
|
|
irq_stat = 0;
|
|
i2c_writel(priv, REG_START, I2C_RS_MUL_CNFG |
|
|
I2C_RS_MUL_TRIG | I2C_TRANSAC_START);
|
|
}
|
|
|
|
if (irq_stat & (I2C_TRANSAC_COMP | restart_flag)) {
|
|
tmo = false;
|
|
if (irq_stat & (I2C_HS_NACKERR | I2C_ACKERR))
|
|
trans_error = 1;
|
|
|
|
break;
|
|
}
|
|
udelay(1);
|
|
if (tmo_poll++ >= TRANSFER_TIMEOUT) {
|
|
tmo = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* clear interrupt mask */
|
|
i2c_writel(priv, REG_INTR_MASK, ~(restart_flag | I2C_HS_NACKERR |
|
|
I2C_ACKERR | I2C_TRANSAC_COMP));
|
|
|
|
if (!tmo && trans_error != 0) {
|
|
if (tmo) {
|
|
ret = -ETIMEDOUT;
|
|
if (!priv->filter_msg)
|
|
debug("I2C timeout! addr: 0x%x,\n", msgs->addr);
|
|
} else {
|
|
ret = -EREMOTEIO;
|
|
if (!priv->filter_msg)
|
|
debug("I2C ACKERR! addr: 0x%x,IRQ:0x%x\n",
|
|
msgs->addr, irq_stat);
|
|
}
|
|
mtk_i2c_init_hw(priv);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* mtk_i2c_transfer
|
|
*
|
|
* @par Description
|
|
* Common i2c transfer API. Set i2c transfer mode according to i2c_msg\n
|
|
* information, then call mtk_i2c_do_transfer() to configure i2c register\n
|
|
* and trigger transfer.
|
|
* @param[in]
|
|
* dev: udevice pointer, struct udevice contains struct mtk_i2c_priv, \n
|
|
* struct mtk_i2c_priv contains register base\n
|
|
* address, operation mode, interrupt status and i2c driver data.
|
|
* @param[in]
|
|
* msgs: i2c_msg pointer, struct i2c_msg contains slave\n
|
|
* address, operation mode, msg length and data buffer.
|
|
* @param[in]
|
|
* num: i2c_msg number.
|
|
* @return
|
|
* i2c_msg number, i2c transfer successfully.\n
|
|
* -EINVAL, msg length is more than 16\n
|
|
* use DMA MODE or slave address more than 0x7f.\n
|
|
* error code from mtk_i2c_init_base().\n
|
|
* error code from mtk_i2c_set_speed().\n
|
|
* error code from mtk_i2c_do_transfer().
|
|
*/
|
|
static int mtk_i2c_transfer(struct udevice *dev, struct i2c_msg *msg,
|
|
int nmsgs)
|
|
{
|
|
struct mtk_i2c_priv *priv = dev_get_priv(dev);
|
|
int left_num;
|
|
uint num_cnt;
|
|
int ret;
|
|
|
|
priv->auto_restart = true;
|
|
left_num = nmsgs;
|
|
if (mtk_i2c_clk_enable(priv))
|
|
return log_msg_ret("transfer enable clk", -1);
|
|
|
|
for (num_cnt = 0; num_cnt < nmsgs; num_cnt++) {
|
|
if (((msg + num_cnt)->addr) > MAX_I2C_ADDR) {
|
|
ret = -EINVAL;
|
|
goto err_exit;
|
|
}
|
|
if ((msg + num_cnt)->len > MAX_I2C_LEN) {
|
|
ret = -EINVAL;
|
|
goto err_exit;
|
|
}
|
|
}
|
|
|
|
/* check if we can skip restart and optimize using WRRD mode */
|
|
if (priv->auto_restart && nmsgs == 2) {
|
|
if (!(msg[0].flags & I2C_M_RD) && (msg[1].flags & I2C_M_RD) &&
|
|
msg[0].addr == msg[1].addr) {
|
|
priv->auto_restart = false;
|
|
}
|
|
}
|
|
|
|
if (priv->auto_restart && nmsgs >= 2 && priv->speed > MAX_FS_MODE_SPEED)
|
|
/* ignore the first restart irq after the master code,
|
|
* otherwise the first transfer will be discarded.
|
|
*/
|
|
priv->ignore_restart_irq = true;
|
|
else
|
|
priv->ignore_restart_irq = false;
|
|
|
|
while (left_num--) {
|
|
/* transfer slave address only to support devices detect */
|
|
if (!msg->buf)
|
|
priv->zero_len = true;
|
|
else
|
|
priv->zero_len = false;
|
|
|
|
if (msg->flags & I2C_M_RD)
|
|
priv->op = I2C_MASTER_RD;
|
|
else
|
|
priv->op = I2C_MASTER_WR;
|
|
|
|
if (!priv->auto_restart) {
|
|
if (nmsgs > 1) {
|
|
/* combined two messages into one transaction */
|
|
priv->op = I2C_MASTER_WRRD;
|
|
left_num--;
|
|
}
|
|
}
|
|
ret = mtk_i2c_do_transfer(priv, msg, nmsgs, left_num);
|
|
if (ret < 0)
|
|
goto err_exit;
|
|
msg++;
|
|
}
|
|
ret = 0;
|
|
|
|
err_exit:
|
|
if (mtk_i2c_clk_disable(priv))
|
|
return log_msg_ret("transfer disable clk", -1);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int mtk_i2c_of_to_plat(struct udevice *dev)
|
|
{
|
|
struct mtk_i2c_priv *priv = dev_get_priv(dev);
|
|
int ret;
|
|
|
|
priv->base = dev_remap_addr_index(dev, 0);
|
|
priv->pdmabase = dev_remap_addr_index(dev, 1);
|
|
ret = clk_get_by_index(dev, 0, &priv->clk_main);
|
|
if (ret)
|
|
return log_msg_ret("clk_get_by_index 0", ret);
|
|
|
|
ret = clk_get_by_index(dev, 1, &priv->clk_dma);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int mtk_i2c_probe(struct udevice *dev)
|
|
{
|
|
struct mtk_i2c_priv *priv = dev_get_priv(dev);
|
|
|
|
priv->soc_data = (struct mtk_i2c_soc_data *)dev_get_driver_data(dev);
|
|
|
|
if (mtk_i2c_clk_enable(priv))
|
|
return log_msg_ret("probe enable clk", -1);
|
|
|
|
mtk_i2c_init_hw(priv);
|
|
|
|
if (mtk_i2c_clk_disable(priv))
|
|
return log_msg_ret("probe disable clk", -1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_i2c_deblock(struct udevice *dev)
|
|
{
|
|
struct mtk_i2c_priv *priv = dev_get_priv(dev);
|
|
|
|
if (mtk_i2c_clk_enable(priv))
|
|
return log_msg_ret("deblock enable clk", -1);
|
|
|
|
mtk_i2c_init_hw(priv);
|
|
|
|
if (mtk_i2c_clk_disable(priv))
|
|
return log_msg_ret("deblock disable clk", -1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct mtk_i2c_soc_data mt76xx_soc_data = {
|
|
.regs = mt_i2c_regs_v1,
|
|
.dma_sync = 0,
|
|
};
|
|
|
|
static const struct mtk_i2c_soc_data mt7981_soc_data = {
|
|
.regs = mt_i2c_regs_v1,
|
|
.dma_sync = 1,
|
|
};
|
|
|
|
static const struct mtk_i2c_soc_data mt7986_soc_data = {
|
|
.regs = mt_i2c_regs_v1,
|
|
.dma_sync = 1,
|
|
};
|
|
|
|
static const struct mtk_i2c_soc_data mt8183_soc_data = {
|
|
.regs = mt_i2c_regs_v2,
|
|
.dma_sync = 1,
|
|
};
|
|
|
|
static const struct mtk_i2c_soc_data mt8518_soc_data = {
|
|
.regs = mt_i2c_regs_v1,
|
|
.dma_sync = 0,
|
|
};
|
|
|
|
static const struct mtk_i2c_soc_data mt8512_soc_data = {
|
|
.regs = mt_i2c_regs_v1,
|
|
.dma_sync = 1,
|
|
};
|
|
|
|
static const struct dm_i2c_ops mtk_i2c_ops = {
|
|
.xfer = mtk_i2c_transfer,
|
|
.set_bus_speed = mtk_i2c_set_speed,
|
|
.deblock = mtk_i2c_deblock,
|
|
};
|
|
|
|
static const struct udevice_id mtk_i2c_ids[] = {
|
|
{
|
|
.compatible = "mediatek,mt7622-i2c",
|
|
.data = (ulong)&mt76xx_soc_data,
|
|
}, {
|
|
.compatible = "mediatek,mt7623-i2c",
|
|
.data = (ulong)&mt76xx_soc_data,
|
|
}, {
|
|
.compatible = "mediatek,mt7629-i2c",
|
|
.data = (ulong)&mt76xx_soc_data,
|
|
}, {
|
|
.compatible = "mediatek,mt7981-i2c",
|
|
.data = (ulong)&mt7981_soc_data,
|
|
}, {
|
|
.compatible = "mediatek,mt7986-i2c",
|
|
.data = (ulong)&mt7986_soc_data,
|
|
}, {
|
|
.compatible = "mediatek,mt8183-i2c",
|
|
.data = (ulong)&mt8183_soc_data,
|
|
}, {
|
|
.compatible = "mediatek,mt8512-i2c",
|
|
.data = (ulong)&mt8512_soc_data,
|
|
}, {
|
|
.compatible = "mediatek,mt8518-i2c",
|
|
.data = (ulong)&mt8518_soc_data,
|
|
}
|
|
};
|
|
|
|
U_BOOT_DRIVER(mtk_i2c) = {
|
|
.name = "mtk_i2c",
|
|
.id = UCLASS_I2C,
|
|
.of_match = mtk_i2c_ids,
|
|
.of_to_plat = mtk_i2c_of_to_plat,
|
|
.probe = mtk_i2c_probe,
|
|
.priv_auto = sizeof(struct mtk_i2c_priv),
|
|
.ops = &mtk_i2c_ops,
|
|
};
|