mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-14 23:33:00 +00:00
dd5f2351e9
Sync the device tree and dt-bindings from Linux v5.6-rc2
11a48a5a18c6 ("Linux 5.6-rc2")
The only exception to this is the mmc pinctrl pin bias of gxl SoC family.
This is a fix which found its way to u-boot but not Linux yet.
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
41 lines
1.3 KiB
Text
41 lines
1.3 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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* Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
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*/
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/dts-v1/;
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#include "meson-g12b-a311d.dtsi"
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#include "meson-khadas-vim3.dtsi"
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#include "meson-g12b-khadas-vim3.dtsi"
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/ {
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compatible = "khadas,vim3", "amlogic,a311d", "amlogic,g12b";
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};
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/*
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* The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
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* lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
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* an USB3.0 Type A connector and a M.2 Key M slot.
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* The PHY driving these differential lines is shared between
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* the USB3.0 controller and the PCIe Controller, thus only
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* a single controller can use it.
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* If the MCU is configured to mux the PCIe/USB3.0 differential lines
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* to the M.2 Key M slot, uncomment the following block to disable
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* USB3.0 from the USB Complex and enable the PCIe controller.
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* The End User is not expected to uncomment the following except for
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* testing purposes, but instead rely on the firmware/bootloader to
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* update these nodes accordingly if PCIe mode is selected by the MCU.
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*/
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/*
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&pcie {
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status = "okay";
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};
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&usb {
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phys = <&usb2_phy0>, <&usb2_phy1>;
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phy-names = "usb2-phy0", "usb2-phy1";
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};
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*/
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