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u-boot/arch/riscv
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Leo Yu-Chi Liang 61d5c543f3 andes: cpu: Enable cache and TLB ECC support 
Andes CPU supports cache and TLB ECC.
Enable them by default.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
2023-12-27 17:29:07 +08:00
..
cpu andes: cpu: Enable cache and TLB ECC support 2023-12-27 17:29:07 +08:00
dts riscv: Extend board compatible string with "qemu,mbv" 2023-12-27 17:29:02 +08:00
include/asm andes: cpu: Enable cache and TLB ECC support 2023-12-27 17:29:07 +08:00
lib riscv: cache: support cache enable in SPL stage 2023-12-27 17:28:57 +08:00
config.mk riscv: Support CONFIG_REMAKE_ELF 2023-04-20 20:45:08 +08:00
Kconfig riscv: Add support for AMD/Xilinx MicroBlaze V 2023-12-18 11:08:49 +08:00
Makefile riscv: Add Zbb support for building U-Boot 2023-10-19 17:29:50 +08:00