mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 17:07:38 +00:00
2c597855aa
Copy the devicetree source for the H2+/H3/H5 SoCs and all existing boards from the Linux v5.18-rc1 tag. To maintain ABI compatibility with existing LTS kernels, one change moving some IP blocks to the r_intc interrupt controller is excluded. This effectively reverts Linux commits 994e5818392c and 9fdef3c3d8c2. This commit also adds the following new board devicetree: - sun8i-h3-nanopi-r1.dts This update should not impact any existing U-Boot functionality. Signed-off-by: Samuel Holland <samuel@sholland.org>
42 lines
847 B
Text
42 lines
847 B
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2018 Chen-Yu Tsai <wens@csie.org>
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*/
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#include "sunxi-bananapi-m2-plus.dtsi"
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/ {
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/*
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* Bananapi M2+ v1.2 uses a GPIO line to change the effective
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* resistance on the CPU regulator's feedback pin.
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*/
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reg_vdd_cpux: vdd-cpux {
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compatible = "regulator-gpio";
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regulator-name = "vdd-cpux";
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regulator-type = "voltage";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <1108475>;
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regulator-max-microvolt = <1308475>;
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regulator-ramp-delay = <50>; /* 4ms */
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gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
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gpios-states = <0x1>;
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states = <1108475 0>, <1308475 1>;
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};
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};
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&cpu0 {
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cpu-supply = <®_vdd_cpux>;
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};
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&cpu1 {
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cpu-supply = <®_vdd_cpux>;
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};
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&cpu2 {
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cpu-supply = <®_vdd_cpux>;
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};
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&cpu3 {
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cpu-supply = <®_vdd_cpux>;
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};
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