mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 17:07:38 +00:00
ceda40a8e6
Update the devicetree files from the Linux kernel, version v6.0-rc4. This is covering the 32-bit SoCs, from arch/arm/boot/dts/. This avoids the not backwards-compatible r_intc binding change, to allow older kernels to boot, but the other nodes are updated. Not much change here, the vast majority is actually cosmetic: node names and using symbolic names for the the RTC clocks. The R40 boards gain DVFS support. Some A23/A33 tablet DTs are unified into a single file. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
621 lines
16 KiB
Text
621 lines
16 KiB
Text
/*
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* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
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* Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/sun6i-rtc.h>
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#include <dt-bindings/clock/sun8i-v3s-ccu.h>
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#include <dt-bindings/reset/sun8i-v3s-ccu.h>
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#include <dt-bindings/clock/sun8i-de2.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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chosen {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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framebuffer-lcd {
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "mixer0-lcd0";
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clocks = <&display_clocks CLK_MIXER0>,
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<&ccu CLK_TCON0>;
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status = "disabled";
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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clocks = <&ccu CLK_CPU>;
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};
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};
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de: display-engine {
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compatible = "allwinner,sun8i-v3s-display-engine";
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allwinner,pipelines = <&mixer0>;
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status = "disabled";
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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osc24M: osc24M_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-accuracy = <50000>;
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clock-output-names = "osc24M";
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};
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osc32k: osc32k_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-accuracy = <50000>;
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clock-output-names = "ext-osc32k";
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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display_clocks: clock@1000000 {
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compatible = "allwinner,sun8i-v3s-de2-clk";
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reg = <0x01000000 0x10000>;
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clocks = <&ccu CLK_BUS_DE>,
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<&ccu CLK_DE>;
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clock-names = "bus",
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"mod";
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resets = <&ccu RST_BUS_DE>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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mixer0: mixer@1100000 {
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compatible = "allwinner,sun8i-v3s-de2-mixer";
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reg = <0x01100000 0x100000>;
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clocks = <&display_clocks 0>,
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<&display_clocks 6>;
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clock-names = "bus",
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"mod";
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resets = <&display_clocks 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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mixer0_out: port@1 {
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reg = <1>;
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mixer0_out_tcon0: endpoint {
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remote-endpoint = <&tcon0_in_mixer0>;
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};
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};
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};
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};
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syscon: system-control@1c00000 {
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compatible = "allwinner,sun8i-v3s-system-control",
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"allwinner,sun8i-h3-system-control";
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reg = <0x01c00000 0xd0>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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};
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nmi_intc: interrupt-controller@1c000d0 {
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compatible = "allwinner,sun8i-v3s-nmi",
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"allwinner,sun9i-a80-nmi";
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x01c000d0 0x0c>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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};
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dma: dma-controller@1c02000 {
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compatible = "allwinner,sun8i-v3s-dma";
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reg = <0x01c02000 0x1000>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_DMA>;
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resets = <&ccu RST_BUS_DMA>;
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#dma-cells = <1>;
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};
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tcon0: lcd-controller@1c0c000 {
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compatible = "allwinner,sun8i-v3s-tcon";
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reg = <0x01c0c000 0x1000>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_TCON0>,
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<&ccu CLK_TCON0>;
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clock-names = "ahb",
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"tcon-ch0";
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clock-output-names = "tcon-pixel-clock";
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#clock-cells = <0>;
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resets = <&ccu RST_BUS_TCON0>;
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reset-names = "lcd";
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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tcon0_in: port@0 {
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reg = <0>;
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tcon0_in_mixer0: endpoint {
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remote-endpoint = <&mixer0_out_tcon0>;
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};
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};
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tcon0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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};
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};
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mmc0: mmc@1c0f000 {
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compatible = "allwinner,sun7i-a20-mmc";
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reg = <0x01c0f000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC0>,
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<&ccu CLK_MMC0>,
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<&ccu CLK_MMC0_OUTPUT>,
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<&ccu CLK_MMC0_SAMPLE>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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resets = <&ccu RST_BUS_MMC0>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc1: mmc@1c10000 {
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compatible = "allwinner,sun7i-a20-mmc";
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reg = <0x01c10000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC1>,
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<&ccu CLK_MMC1>,
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<&ccu CLK_MMC1_OUTPUT>,
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<&ccu CLK_MMC1_SAMPLE>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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resets = <&ccu RST_BUS_MMC1>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc1_pins>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc2: mmc@1c11000 {
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compatible = "allwinner,sun7i-a20-mmc";
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reg = <0x01c11000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC2>,
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<&ccu CLK_MMC2>,
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<&ccu CLK_MMC2_OUTPUT>,
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<&ccu CLK_MMC2_SAMPLE>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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resets = <&ccu RST_BUS_MMC2>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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crypto@1c15000 {
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compatible = "allwinner,sun8i-v3s-crypto",
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"allwinner,sun8i-a33-crypto";
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reg = <0x01c15000 0x1000>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
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clock-names = "ahb", "mod";
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dmas = <&dma 16>, <&dma 16>;
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dma-names = "rx", "tx";
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resets = <&ccu RST_BUS_CE>;
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reset-names = "ahb";
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};
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usb_otg: usb@1c19000 {
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compatible = "allwinner,sun8i-h3-musb";
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reg = <0x01c19000 0x0400>;
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clocks = <&ccu CLK_BUS_OTG>;
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resets = <&ccu RST_BUS_OTG>;
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "mc";
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phys = <&usbphy 0>;
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phy-names = "usb";
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extcon = <&usbphy 0>;
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status = "disabled";
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};
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usbphy: phy@1c19400 {
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compatible = "allwinner,sun8i-v3s-usb-phy";
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reg = <0x01c19400 0x2c>,
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<0x01c1a800 0x4>;
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reg-names = "phy_ctrl",
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"pmu0";
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clocks = <&ccu CLK_USB_PHY0>;
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clock-names = "usb0_phy";
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resets = <&ccu RST_USB_PHY0>;
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reset-names = "usb0_reset";
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status = "disabled";
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#phy-cells = <1>;
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};
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ccu: clock@1c20000 {
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compatible = "allwinner,sun8i-v3s-ccu";
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reg = <0x01c20000 0x400>;
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clocks = <&osc24M>, <&rtc CLK_OSC32K>;
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clock-names = "hosc", "losc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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rtc: rtc@1c20400 {
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#clock-cells = <1>;
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compatible = "allwinner,sun8i-v3-rtc";
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reg = <0x01c20400 0x54>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&osc32k>;
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clock-output-names = "osc32k", "osc32k-out";
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};
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pio: pinctrl@1c20800 {
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compatible = "allwinner,sun8i-v3s-pinctrl";
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reg = <0x01c20800 0x400>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
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<&rtc CLK_OSC32K>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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#gpio-cells = <3>;
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interrupt-controller;
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#interrupt-cells = <3>;
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/omit-if-no-ref/
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csi0_mclk_pin: csi0-mclk-pin {
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pins = "PE20";
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function = "csi_mipi";
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};
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/omit-if-no-ref/
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csi1_8bit_pins: csi1-8bit-pins {
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pins = "PE0", "PE2", "PE3", "PE8", "PE9",
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"PE10", "PE11", "PE12", "PE13", "PE14",
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"PE15";
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function = "csi";
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};
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/omit-if-no-ref/
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csi1_mclk_pin: csi1-mclk-pin {
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pins = "PE1";
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function = "csi";
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};
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i2c0_pins: i2c0-pins {
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pins = "PB6", "PB7";
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function = "i2c0";
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};
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/omit-if-no-ref/
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i2c1_pb_pins: i2c1-pb-pins {
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pins = "PB8", "PB9";
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function = "i2c1";
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};
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/omit-if-no-ref/
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i2c1_pe_pins: i2c1-pe-pins {
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pins = "PE21", "PE22";
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function = "i2c1";
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};
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uart0_pb_pins: uart0-pb-pins {
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pins = "PB8", "PB9";
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function = "uart0";
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};
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uart2_pins: uart2-pins {
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pins = "PB0", "PB1";
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function = "uart2";
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};
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mmc0_pins: mmc0-pins {
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pins = "PF0", "PF1", "PF2", "PF3",
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"PF4", "PF5";
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function = "mmc0";
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drive-strength = <30>;
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bias-pull-up;
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};
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mmc1_pins: mmc1-pins {
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pins = "PG0", "PG1", "PG2", "PG3",
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"PG4", "PG5";
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function = "mmc1";
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drive-strength = <30>;
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bias-pull-up;
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};
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spi0_pins: spi0-pins {
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pins = "PC0", "PC1", "PC2", "PC3";
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function = "spi0";
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};
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};
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timer@1c20c00 {
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compatible = "allwinner,sun8i-v3s-timer";
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reg = <0x01c20c00 0xa0>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&osc24M>;
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};
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wdt0: watchdog@1c20ca0 {
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compatible = "allwinner,sun6i-a31-wdt";
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reg = <0x01c20ca0 0x20>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&osc24M>;
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};
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pwm: pwm@1c21400 {
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compatible = "allwinner,sun8i-v3s-pwm",
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"allwinner,sun7i-a20-pwm";
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reg = <0x01c21400 0xc>;
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clocks = <&osc24M>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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lradc: lradc@1c22800 {
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compatible = "allwinner,sun4i-a10-lradc-keys";
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reg = <0x01c22800 0x400>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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codec: codec@1c22c00 {
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#sound-dai-cells = <0>;
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compatible = "allwinner,sun8i-v3s-codec";
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reg = <0x01c22c00 0x400>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
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clock-names = "apb", "codec";
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resets = <&ccu RST_BUS_CODEC>;
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dmas = <&dma 15>, <&dma 15>;
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dma-names = "rx", "tx";
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allwinner,codec-analog-controls = <&codec_analog>;
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status = "disabled";
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};
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|
codec_analog: codec-analog@1c23000 {
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compatible = "allwinner,sun8i-v3s-codec-analog";
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|
reg = <0x01c23000 0x4>;
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};
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uart0: serial@1c28000 {
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compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28000 0x400>;
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_BUS_UART0>;
|
|
dmas = <&dma 6>, <&dma 6>;
|
|
dma-names = "rx", "tx";
|
|
resets = <&ccu RST_BUS_UART0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@1c28400 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28400 0x400>;
|
|
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_BUS_UART1>;
|
|
dmas = <&dma 7>, <&dma 7>;
|
|
dma-names = "rx", "tx";
|
|
resets = <&ccu RST_BUS_UART1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@1c28800 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28800 0x400>;
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_BUS_UART2>;
|
|
dmas = <&dma 8>, <&dma 8>;
|
|
dma-names = "rx", "tx";
|
|
resets = <&ccu RST_BUS_UART2>;
|
|
pinctrl-0 = <&uart2_pins>;
|
|
pinctrl-names = "default";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@1c2ac00 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x01c2ac00 0x400>;
|
|
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_I2C0>;
|
|
resets = <&ccu RST_BUS_I2C0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_pins>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c1: i2c@1c2b000 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x01c2b000 0x400>;
|
|
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_I2C1>;
|
|
resets = <&ccu RST_BUS_I2C1>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
emac: ethernet@1c30000 {
|
|
compatible = "allwinner,sun8i-v3s-emac";
|
|
syscon = <&syscon>;
|
|
reg = <0x01c30000 0x10000>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
resets = <&ccu RST_BUS_EMAC>;
|
|
reset-names = "stmmaceth";
|
|
clocks = <&ccu CLK_BUS_EMAC>;
|
|
clock-names = "stmmaceth";
|
|
phy-handle = <&int_mii_phy>;
|
|
phy-mode = "mii";
|
|
status = "disabled";
|
|
|
|
mdio: mdio {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "snps,dwmac-mdio";
|
|
};
|
|
|
|
mdio_mux: mdio-mux {
|
|
compatible = "allwinner,sun8i-h3-mdio-mux";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
mdio-parent-bus = <&mdio>;
|
|
/* Only one MDIO is usable at the time */
|
|
internal_mdio: mdio@1 {
|
|
compatible = "allwinner,sun8i-h3-mdio-internal";
|
|
reg = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
int_mii_phy: ethernet-phy@1 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <1>;
|
|
clocks = <&ccu CLK_BUS_EPHY>;
|
|
resets = <&ccu RST_BUS_EPHY>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
spi0: spi@1c68000 {
|
|
compatible = "allwinner,sun8i-h3-spi";
|
|
reg = <0x01c68000 0x1000>;
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
|
|
clock-names = "ahb", "mod";
|
|
dmas = <&dma 23>, <&dma 23>;
|
|
dma-names = "rx", "tx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi0_pins>;
|
|
resets = <&ccu RST_BUS_SPI0>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
gic: interrupt-controller@1c81000 {
|
|
compatible = "arm,gic-400";
|
|
reg = <0x01c81000 0x1000>,
|
|
<0x01c82000 0x2000>,
|
|
<0x01c84000 0x2000>,
|
|
<0x01c86000 0x2000>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
};
|
|
|
|
csi1: camera@1cb4000 {
|
|
compatible = "allwinner,sun8i-v3s-csi";
|
|
reg = <0x01cb4000 0x3000>;
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_CSI>,
|
|
<&ccu CLK_CSI1_SCLK>,
|
|
<&ccu CLK_DRAM_CSI>;
|
|
clock-names = "bus", "mod", "ram";
|
|
resets = <&ccu RST_BUS_CSI>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|