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505efde27a
The NXP i.MXRT1170 Evaluation Kit (EVK) provides a platform for rapid evaluation of the i.MXRT, which features NXP's implementation of the Arm Cortex-M7 and Cortex-M4 core. The EVK provides 64 MB SDRAM, Micro SD card socket, USB 2.0 OTG. This patch aims to support the preliminary booting up features as follows: GPIO LPUART SD/MMC SDRAM Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
250 lines
5.8 KiB
Text
250 lines
5.8 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) 2022
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* Author(s): Jesse Taube <Mr.Bossman075@gmail.com>
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* Giulio Benetti <giulio.benetti@benettiengineering.com>
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*/
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/dts-v1/;
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#include "imxrt1170.dtsi"
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#include "imxrt1170-evk-u-boot.dtsi"
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#include "imxrt1170-pinfunc.h"
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/ {
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model = "NXP imxrt1170-evk board";
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compatible = "fsl,imxrt1170-evk", "fsl,imxrt1170";
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chosen {
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stdout-path = "serial0:115200n8";
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tick-timer = &gpt1;
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};
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memory {
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device_type = "memory";
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reg = <0x20240000 0xf0000 0x80000000 0x4000000>;
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ocram: ocram@20240000 {
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device_type = "memory";
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reg = <0x20240000 0xf0000>;
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};
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sdram: sdram@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x4000000>;
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};
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};
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};
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&lpuart1 { /* console */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart1>;
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status = "okay";
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};
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&semc {
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/*
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* Memory configuration from sdram datasheet IS42S16160J-6BLI
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*/
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fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
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0
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0
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0
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0
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0>;
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fsl,sdram-control = /bits/ 8 <MEM_WIDTH_32BITS
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BL_8
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COL_9BITS
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CL_3>;
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fsl,sdram-timing = /bits/ 8 <0x2
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0x2
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0xd
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0x0
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0x8
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0x7
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0x0d
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0x0b
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0x00
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0x00
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0x00
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0x0A
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0x08
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0x09>;
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bank1: bank@0 {
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fsl,base-address = <0x80000000>;
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fsl,memory-size = <MEM_SIZE_64M>;
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart1>;
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imxrt1170-evk {
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pinctrl_lpuart1: lpuart1grp {
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fsl,pins = <
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IOMUXC_GPIO_AD_24_LPUART1_TXD 0xf1
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IOMUXC_GPIO_AD_25_LPUART1_RXD 0xf1
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>;
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};
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pinctrl_usdhc0: usdhc0grp {
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fsl,pins = <
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IOMUXC_GPIO_AD_32_USDHC1_CD_B
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0x1B000
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IOMUXC_GPIO_AD_34_USDHC1_VSELECT
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0xB069
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IOMUXC_GPIO_SD_B1_00_USDHC1_CMD
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0x17061
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IOMUXC_GPIO_SD_B1_01_USDHC1_CLK
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0x17061
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IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3
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0x17061
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IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2
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0x17061
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IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1
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0x17061
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IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0
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0x17061
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>;
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};
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pinctrl_semc: semcgrp {
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fsl,pins = <
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IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00
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8 /* SEMC_D0 */
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IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01
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8 /* SEMC_D1 */
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IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02
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8 /* SEMC_D2 */
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IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03
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8 /* SEMC_D3 */
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IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04
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8 /* SEMC_D4 */
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IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05
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8 /* SEMC_D5 */
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IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06
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8 /* SEMC_D6 */
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IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07
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8 /* SEMC_D7 */
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IOMUXC_GPIO_EMC_B1_08_SEMC_DM00
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8 /* SEMC_DM0 */
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IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00
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8 /* SEMC_A0 */
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IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01
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8 /* SEMC_A1 */
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IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02
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8 /* SEMC_A2 */
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IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03
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8 /* SEMC_A3 */
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IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04
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8 /* SEMC_A4 */
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IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05
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8 /* SEMC_A5 */
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IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06
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8 /* SEMC_A6 */
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IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07
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8 /* SEMC_A7 */
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IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08
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8 /* SEMC_A8 */
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IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09
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8 /* SEMC_A9 */
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IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11
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8 /* SEMC_A11 */
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IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12
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8 /* SEMC_A12 */
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IOMUXC_GPIO_EMC_B1_21_SEMC_BA0
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8 /* SEMC_BA0 */
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IOMUXC_GPIO_EMC_B1_22_SEMC_BA1
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8 /* SEMC_BA1 */
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IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10
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8 /* SEMC_A10 */
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IOMUXC_GPIO_EMC_B1_24_SEMC_CAS
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8 /* SEMC_CAS */
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IOMUXC_GPIO_EMC_B1_25_SEMC_RAS
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8 /* SEMC_RAS */
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IOMUXC_GPIO_EMC_B1_26_SEMC_CLK
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8 /* SEMC_CLK */
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IOMUXC_GPIO_EMC_B1_27_SEMC_CKE
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8 /* SEMC_CKE */
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IOMUXC_GPIO_EMC_B1_28_SEMC_WE
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8 /* SEMC_WE */
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IOMUXC_GPIO_EMC_B1_29_SEMC_CS0
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8 /* SEMC_CS0 */
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IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08
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8 /* SEMC_D8 */
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IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09
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8 /* SEMC_D9 */
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IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10
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8 /* SEMC_D10 */
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IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11
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8 /* SEMC_D11 */
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IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12
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8 /* SEMC_D12 */
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IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13
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8 /* SEMC_D13 */
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IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14
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8 /* SEMC_D14 */
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IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15
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8 /* SEMC_D15 */
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IOMUXC_GPIO_EMC_B1_08_SEMC_DM00
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8 /* SEMC_DM00 */
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IOMUXC_GPIO_EMC_B1_38_SEMC_DM01
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8 /* SEMC_DM01 */
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IOMUXC_GPIO_EMC_B2_08_SEMC_DM02
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4 /* SEMC_DM02 */
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IOMUXC_GPIO_EMC_B2_17_SEMC_DM03
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8 /* SEMC_DM03 */
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IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16
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8 /* SEMC_D16 */
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IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17
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8 /* SEMC_D17 */
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IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18
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8 /* SEMC_D18 */
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IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19
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8 /* SEMC_D19 */
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IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20
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8 /* SEMC_D20 */
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IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21
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8 /* SEMC_D21 */
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IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22
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8 /* SEMC_D22 */
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IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23
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8 /* SEMC_D23 */
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IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24
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8 /* SEMC_D24 */
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IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25
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8 /* SEMC_D25 */
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IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26
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4 /* SEMC_D26 */
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IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27
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8 /* SEMC_D27 */
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IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28
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8 /* SEMC_D28 */
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IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29
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8 /* SEMC_D29 */
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IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30
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8 /* SEMC_D30 */
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IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31
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8 /* SEMC_D31 */
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IOMUXC_GPIO_EMC_B1_39_SEMC_DQS
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(IMX_PAD_SION | 8) /* SEMC_DQS */
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>;
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};
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};
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};
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&gpt1 {
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
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pinctrl-0 = <&pinctrl_usdhc0>;
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pinctrl-1 = <&pinctrl_usdhc0>;
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pinctrl-2 = <&pinctrl_usdhc0>;
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pinctrl-3 = <&pinctrl_usdhc0>;
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status = "okay";
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broken-cd;
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};
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