mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 17:07:38 +00:00
38d1a18750
Add properties related to eMMC HS400 mode for esdhc1. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
64 lines
1.1 KiB
Text
64 lines
1.1 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
|
/*
|
|
* NXP LX2162AQDS device tree source for the SERDES block #1 - protocol 17
|
|
*
|
|
* Some assumptions are made:
|
|
* * mezzanine card M8 is connected to IO SLOT1 (25g-aui for DPMAC 3,4,5,6)
|
|
*
|
|
* Copyright 2020-2021 NXP
|
|
*
|
|
*/
|
|
|
|
#include "fsl-lx2160a-qds.dtsi"
|
|
|
|
&dpmac3 {
|
|
status = "okay";
|
|
phy-handle = <&inphi_phy0>;
|
|
phy-connection-type = "25g-aui";
|
|
};
|
|
|
|
&dpmac4 {
|
|
status = "okay";
|
|
phy-handle = <&inphi_phy1>;
|
|
phy-connection-type = "25g-aui";
|
|
};
|
|
|
|
&dpmac5 {
|
|
status = "okay";
|
|
phy-handle = <&inphi_phy2>;
|
|
phy-connection-type = "25g-aui";
|
|
};
|
|
|
|
&dpmac6 {
|
|
status = "okay";
|
|
phy-handle = <&inphi_phy3>;
|
|
phy-connection-type = "25g-aui";
|
|
};
|
|
|
|
&emdio1_slot1 {
|
|
inphi_phy0: ethernet-phy@0 {
|
|
compatible = "ethernet-phy-id0210.7440";
|
|
reg = <0x0>;
|
|
};
|
|
|
|
inphi_phy1: ethernet-phy@1 {
|
|
compatible = "ethernet-phy-id0210.7440";
|
|
reg = <0x1>;
|
|
};
|
|
|
|
inphi_phy2: ethernet-phy@2 {
|
|
compatible = "ethernet-phy-id0210.7440";
|
|
reg = <0x2>;
|
|
};
|
|
|
|
inphi_phy3: ethernet-phy@3 {
|
|
compatible = "ethernet-phy-id0210.7440";
|
|
reg = <0x3>;
|
|
};
|
|
};
|
|
|
|
&esdhc1 {
|
|
mmc-hs200-1_8v;
|
|
mmc-hs400-1_8v;
|
|
bus-width = <8>;
|
|
};
|