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https://github.com/AsahiLinux/u-boot
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703b84ec29
At present U-Boot SPL fails to boot on SiFive Unleashed board, due to a load address misaligned exception happens when loading the FIT image in spl_load_simple_fit(). The exception happens in memmove() which is called by fdt_splice_(). Commit8f0dc4cfd1introduces an assembly version of memmove but it does take misalignment into account (it checks if length is a multiple of machine word size but pointers need also be aligned). As a result it will generate misaligned load/store for the majority of cases and causes significant performance regression on hardware that traps misaligned load/store and emulate them using firmware. The current behaviour of memcpy is that it checks if both src and dest pointers are co-aligned (aka congruent modular SZ_REG). If aligned, it will copy data word-by-word after first aligning pointers to word boundary. If src and dst are not co-aligned, however, byte-wise copy will be performed. This patch was taken from the Linux kernel patch [1], which has not been applied at the time being. It fixes the memmove and optimises memcpy for misaligned cases. It will first align destination pointer to word-boundary regardless whether src and dest are co-aligned or not. If they indeed are, then wordwise copy is performed. If they are not co-aligned, then it will load two adjacent words from src and use shifts to assemble a full machine word. Some additional assembly level micro-optimisation is also performed to ensure more instructions can be compressed (e.g. prefer a0 to t6). With this patch, U-Boot boots again on SiFive Unleashed board. [1] https://patchwork.kernel.org/project/linux-riscv/patch/20210216225555.4976-1-gary@garyguo.net/ Fixes:8f0dc4cfd1("riscv: assembler versions of memcpy, memmove, memset") Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
128 lines
2.6 KiB
ArmAsm
128 lines
2.6 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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#include <linux/linkage.h>
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#include <asm/asm.h>
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ENTRY(__memmove)
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WEAK(memmove)
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/*
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* Here we determine if forward copy is possible. Forward copy is
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* preferred to backward copy as it is more cache friendly.
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*
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* If a0 >= a1, t0 gives their distance, if t0 >= a2 then we can
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* copy forward.
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* If a0 < a1, we can always copy forward. This will make t0 negative,
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* so a *unsigned* comparison will always have t0 >= a2.
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*
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* For forward copy we just delegate the task to memcpy.
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*/
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sub t0, a0, a1
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bltu t0, a2, 1f
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tail __memcpy
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1:
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/*
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* Register allocation for code below:
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* a0 - end of uncopied dst
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* a1 - end of uncopied src
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* t0 - start of uncopied dst
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*/
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mv t0, a0
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add a0, a0, a2
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add a1, a1, a2
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/*
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* Use bytewise copy if too small.
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*
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* This threshold must be at least 2*SZREG to ensure at least one
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* wordwise copy is performed. It is chosen to be 16 because it will
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* save at least 7 iterations of bytewise copy, which pays off the
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* fixed overhead.
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*/
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li a3, 16
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bltu a2, a3, .Lbyte_copy_tail
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/*
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* Bytewise copy first to align t0 to word boundary.
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*/
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andi a2, a0, ~(SZREG-1)
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beq a0, a2, 2f
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1:
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addi a1, a1, -1
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lb a5, 0(a1)
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addi a0, a0, -1
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sb a5, 0(a0)
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bne a0, a2, 1b
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2:
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/*
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* Now a0 is word-aligned. If a1 is also word aligned, we could perform
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* aligned word-wise copy. Otherwise we need to perform misaligned
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* word-wise copy.
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*/
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andi a3, a1, SZREG-1
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bnez a3, .Lmisaligned_word_copy
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/* Wordwise copy */
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addi t0, t0, SZREG-1
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bleu a0, t0, 2f
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1:
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addi a1, a1, -SZREG
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REG_L a5, 0(a1)
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addi a0, a0, -SZREG
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REG_S a5, 0(a0)
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bgtu a0, t0, 1b
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2:
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addi t0, t0, -(SZREG-1)
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.Lbyte_copy_tail:
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/*
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* Bytewise copy anything left.
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*/
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beq a0, t0, 2f
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1:
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addi a1, a1, -1
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lb a5, 0(a1)
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addi a0, a0, -1
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sb a5, 0(a0)
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bne a0, t0, 1b
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2:
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mv a0, t0
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ret
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.Lmisaligned_word_copy:
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/*
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* Misaligned word-wise copy.
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* For misaligned copy we still perform word-wise copy, but we need to
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* use the value fetched from the previous iteration and do some shifts.
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* This is safe because we wouldn't access more words than necessary.
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*/
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/* Calculate shifts */
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slli t3, a3, 3
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sub t4, x0, t3 /* negate is okay as shift will only look at LSBs */
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/* Load the initial value and align a1 */
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andi a1, a1, ~(SZREG-1)
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REG_L a5, 0(a1)
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addi t0, t0, SZREG-1
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/* At least one iteration will be executed here, no check */
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1:
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sll a4, a5, t4
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addi a1, a1, -SZREG
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REG_L a5, 0(a1)
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srl a2, a5, t3
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or a2, a2, a4
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addi a0, a0, -SZREG
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REG_S a2, 0(a0)
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bgtu a0, t0, 1b
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/* Update pointers to correct value */
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addi t0, t0, -(SZREG-1)
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add a1, a1, a3
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j .Lbyte_copy_tail
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END(__memmove)
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