mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 06:00:43 +00:00
7ffe3cd62e
Since CONFIG_OF_BOARD_SETUP depends on CONFIG_OF_LIBFDT:
config OF_BOARD_SETUP
bool "Set up board-specific details in device tree before boot"
depends on OF_LIBFDT
...
remove superfluous tests of CONFIG_OF_LIBFDT when testing for
CONFIG_OF_BOARD_SETUP.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
[trini: Typo fix: s/ifdefi/ifdef/]
Signed-off-by: Tom Rini <trini@konsulko.com>
507 lines
12 KiB
C
507 lines
12 KiB
C
/*
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* (C) Copyright 2009
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* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <console.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/ppc4xx-gpio.h>
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#include <asm/4xx_pci.h>
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#include <command.h>
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#include <malloc.h>
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/*
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* PMC405-DE cpld registers
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* - all registers are 8 bit
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* - all registers are on 32 bit addesses
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*/
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struct pmc405de_cpld {
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/* cpld design version */
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u8 version;
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u8 reserved0[3];
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/* misc. status lines */
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u8 status;
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u8 reserved1[3];
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/*
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* gated control flags
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* gate bit(s) must be written with '1' to
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* access control flag
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*/
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u8 control;
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u8 reserved2[3];
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};
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#define CPLD_VERSION_MASK 0x0f
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#define CPLD_CONTROL_POSTLED_N 0x01
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#define CPLD_CONTROL_POSTLED_GATE 0x02
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#define CPLD_CONTROL_RESETOUT_N 0x40
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#define CPLD_CONTROL_RESETOUT_N_GATE 0x80
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DECLARE_GLOBAL_DATA_PTR;
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extern void __ft_board_setup(void *blob, bd_t *bd);
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extern void pll_write(u32 a, u32 b);
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static int wait_for_pci_ready_done;
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static int is_monarch(void);
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static int pci_is_66mhz(void);
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static int board_revision(void);
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static int cpld_revision(void);
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static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div);
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int board_early_init_f(void)
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{
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u32 pllmr0, pllmr1;
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/*
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* check M66EN and patch PLB:PCI divider for 66MHz PCI
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*
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* fCPU==333MHz && fPCI==66MHz (PLBDiv==3 && M66EN==1): PLB/PCI=1
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* fCPU==333MHz && fPCI==33MHz (PLBDiv==3 && M66EN==0): PLB/PCI=2
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* fCPU==133|266MHz && fPCI==66MHz (PLBDiv==1|2 && M66EN==1): PLB/PCI=2
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* fCPU==133|266MHz && fPCI==33MHz (PLBDiv==1|2 && M66EN==0): PLB/PCI=3
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*
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* calling upd_plb_pci_div() may end in calling pll_write() which will
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* do a chip reset and never return.
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*/
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pllmr0 = mfdcr(CPC0_PLLMR0);
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pllmr1 = mfdcr(CPC0_PLLMR1);
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if ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) == PLLMR0_CPU_PLB_DIV_3) {
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/* fCPU=333MHz, fPLB=111MHz */
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if (pci_is_66mhz())
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upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_1);
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else
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upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2);
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} else {
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/* fCPU=133|266MHz, fPLB=133MHz */
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if (pci_is_66mhz())
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upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2);
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else
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upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_3);
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}
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/*
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* IRQ 25 (EXT IRQ 0) PCI-INTA#; active low; level sensitive
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* IRQ 26 (EXT IRQ 1) PCI-INTB#; active low; level sensitive
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* IRQ 27 (EXT IRQ 2) PCI-INTC#; active low; level sensitive
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* IRQ 28 (EXT IRQ 3) PCI-INTD#; active low; level sensitive
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* IRQ 29 (EXT IRQ 4) ETH0-PHY-IRQ#; active low; level sensitive
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* IRQ 30 (EXT IRQ 5) ETH1-PHY-IRQ#; active low; level sensitive
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* IRQ 31 (EXT IRQ 6) PLD-IRQ#; active low; level sensitive
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*/
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mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
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mtdcr(UIC0ER, 0x00000000); /* disable all ints */
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mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
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mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
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mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
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mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest prio */
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mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
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/*
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* EBC Configuration Register:
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* - set ready timeout to 512 ebc-clks -> ca. 15 us
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* - EBC lines are always driven
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*/
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mtebc(EBC0_CFG, 0xa8400000);
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return 0;
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}
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static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div)
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{
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if ((pllmr0 & PLLMR0_PCI_TO_PLB_MASK) != div)
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pll_write((pllmr0 & ~PLLMR0_PCI_TO_PLB_MASK) | div, pllmr1);
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}
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int misc_init_r(void)
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{
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int i;
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struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
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struct pmc405de_cpld *cpld =
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(struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
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if (!is_monarch()) {
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/* PCI configuration done: release EREADY */
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setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EREADY);
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setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_EREADY);
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}
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/* turn off POST LED */
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out_8(&cpld->control,
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CPLD_CONTROL_POSTLED_N | CPLD_CONTROL_POSTLED_GATE);
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/* turn on LEDs: RUN, A, B */
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clrbits_be32(&gpio0->or,
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CONFIG_SYS_GPIO_LEDRUN_N |
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CONFIG_SYS_GPIO_LEDA_N |
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CONFIG_SYS_GPIO_LEDB_N);
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for (i=0; i < 200; i++)
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udelay(1000);
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/* turn off LEDs: A, B */
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setbits_be32(&gpio0->or,
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CONFIG_SYS_GPIO_LEDA_N |
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CONFIG_SYS_GPIO_LEDB_N);
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return (0);
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}
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static int is_monarch(void)
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{
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struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
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return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_MONARCH_N) == 0;
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}
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static int pci_is_66mhz(void)
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{
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struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
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return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_M66EN);
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}
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static int board_revision(void)
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{
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struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
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return ((in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_HWREV_MASK) >>
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CONFIG_SYS_GPIO_HWREV_SHIFT);
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}
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static int cpld_revision(void)
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{
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struct pmc405de_cpld *cpld =
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(struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
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return ((in_8(&cpld->version) & CPLD_VERSION_MASK));
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}
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/*
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* Check Board Identity
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*/
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int checkboard(void)
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{
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puts("Board: esd GmbH - PMC-CPU/405-DE");
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gd->board_type = board_revision();
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printf(", Rev 1.%ld, ", gd->board_type);
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if (!is_monarch())
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puts("non-");
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printf("monarch, PCI=%s MHz, PLD-Rev 1.%d\n",
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pci_is_66mhz() ? "66" : "33", cpld_revision());
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return 0;
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}
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static void wait_for_pci_ready(void)
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{
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struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
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int i;
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char *s = getenv("pcidelay");
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/* only wait once */
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if (wait_for_pci_ready_done)
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return;
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/*
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* We have our own handling of the pcidelay variable.
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* Using CONFIG_PCI_BOOTDELAY enables pausing for host
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* and adapter devices. For adapter devices we do not
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* want this.
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*/
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if (s) {
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int ms = simple_strtoul(s, NULL, 10);
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printf("PCI: Waiting for %d ms\n", ms);
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for (i=0; i<ms; i++)
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udelay(1000);
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}
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if (!(in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY)) {
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printf("PCI: Waiting for EREADY (CTRL-C to skip) ... ");
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while (1) {
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if (ctrlc()) {
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puts("abort\n");
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break;
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}
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if (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY) {
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printf("done\n");
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break;
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}
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}
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}
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wait_for_pci_ready_done = 1;
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}
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/*
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* Overwrite weak is_pci_host()
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*
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* This routine is called to determine if a pci scan should be
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* performed. With various hardware environments (especially cPCI and
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* PPMC) it's insufficient to depend on the state of the arbiter enable
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* bit in the strap register, or generic host/adapter assumptions.
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*
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* Return 0 for adapter mode, non-zero for host (monarch) mode.
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*/
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int is_pci_host(struct pci_controller *hose)
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{
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char *s;
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if (!is_monarch()) {
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/*
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* Overwrite PCI identification when running in
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* non-monarch mode
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* This should be moved into pci_target_init()
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* when it is sometimes available for 405 CPUs
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*/
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pci_write_config_word(PCIDEVID_405GP,
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PCI_SUBSYSTEM_ID,
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CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
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pci_write_config_word(PCIDEVID_405GP,
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PCI_CLASS_SUB_CODE,
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CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
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}
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s = getenv("pciscan");
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if (s == NULL) {
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if (is_monarch()) {
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wait_for_pci_ready();
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return 1;
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} else {
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return 0;
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}
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} else {
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if (!strcmp(s, "yes"))
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return 1;
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}
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return 0;
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}
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/*
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* Overwrite weak pci_pre_init()
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*
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* The default implementation enables the 405EP
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* internal PCI arbiter. We do not want that
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* on a PMC module.
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*/
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int pci_pre_init(struct pci_controller *hose)
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{
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return 1;
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}
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#ifdef CONFIG_OF_BOARD_SETUP
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int ft_board_setup(void *blob, bd_t *bd)
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{
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int rc;
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__ft_board_setup(blob, bd);
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/*
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* Disable PCI in non-monarch mode.
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*/
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if (!is_monarch()) {
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rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
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"disabled", sizeof("disabled"), 1);
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if (rc) {
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printf("Unable to update property status in PCI node, "
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"err=%s\n",
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fdt_strerror(rc));
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}
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}
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return 0;
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}
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#endif /* CONFIG_OF_BOARD_SETUP */
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#if defined(CONFIG_SYS_EEPROM_WREN)
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/* Input: <dev_addr> I2C address of EEPROM device to enable.
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* <state> -1: deliver current state
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* 0: disable write
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* 1: enable write
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* Returns: -1: wrong device address
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* 0: dis-/en- able done
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* 0/1: current state if <state> was -1.
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*/
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int eeprom_write_enable(unsigned dev_addr, int state)
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{
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struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
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if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
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return -1;
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} else {
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switch (state) {
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case 1:
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/* Enable write access, clear bit GPIO0. */
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clrbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP);
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state = 0;
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break;
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case 0:
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/* Disable write access, set bit GPIO0. */
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setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP);
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state = 0;
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break;
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default:
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/* Read current status back. */
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state = (0 == (in_be32(&gpio0->or) &
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CONFIG_SYS_GPIO_EEPROM_WP));
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break;
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}
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}
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return state;
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}
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int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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int query = argc == 1;
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int state = 0;
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if (query) {
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/* Query write access state. */
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state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, - 1);
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if (state < 0) {
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puts("Query of write access state failed.\n");
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} else {
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printf("Write access for device 0x%0x is %sabled.\n",
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CONFIG_SYS_I2C_EEPROM_ADDR,
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state ? "en" : "dis");
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state = 0;
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}
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} else {
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if ('0' == argv[1][0]) {
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/* Disable write access. */
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state = eeprom_write_enable(
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CONFIG_SYS_I2C_EEPROM_ADDR, 0);
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} else {
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/* Enable write access. */
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state = eeprom_write_enable(
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CONFIG_SYS_I2C_EEPROM_ADDR, 1);
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}
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if (state < 0)
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puts ("Setup of write access state failed.\n");
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}
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return state;
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}
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U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
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"Enable / disable / query EEPROM write access",
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""
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);
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#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
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#if defined(CONFIG_PRAM)
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#include <environment.h>
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int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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u32 pram, nextbase, base;
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char *v;
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u32 param;
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ulong *lptr;
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v = getenv("pram");
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if (v)
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pram = simple_strtoul(v, NULL, 10);
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else {
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printf("Error: pram undefined. Please define pram in KiB\n");
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return 1;
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}
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base = gd->bd->bi_memsize;
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#if defined(CONFIG_LOGBUFFER)
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base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
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#endif
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/*
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* gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MM_TOP_HIDE
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*/
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param = base - (pram << 10);
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printf("PARAM: @%08x\n", param);
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debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->bd->bi_memsize, base);
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/* clear entire PA ram */
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memset((void*)param, 0, (pram << 10));
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/* reserve 4k for pointer field */
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nextbase = base - 4096;
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lptr = (ulong*)(base);
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/*
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* *(--lptr) = item_size;
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* *(--lptr) = base - item_base = distance from field top;
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*/
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/* env is first (4k aligned) */
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nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
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memcpy((void*)nextbase, env_ptr, CONFIG_ENV_SIZE);
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*(--lptr) = CONFIG_ENV_SIZE; /* size */
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*(--lptr) = base - nextbase; /* offset | type=0 */
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/* free section */
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*(--lptr) = nextbase - param; /* size */
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*(--lptr) = (base - param) | 126; /* offset | type=126 */
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/* terminate pointer field */
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*(--lptr) = crc32(0, (void*)(base - 0x10), 0x10);
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*(--lptr) = 0; /* offset=0 -> terminator */
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return 0;
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}
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U_BOOT_CMD(
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painit, 1, 1, do_painit,
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"prepare PciAccess system",
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""
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);
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#endif /* CONFIG_PRAM */
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int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
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setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_SELFRST_N);
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return 0;
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}
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U_BOOT_CMD(
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selfreset, 1, 1, do_selfreset,
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"assert self-reset# signal",
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""
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);
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int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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struct pmc405de_cpld *cpld =
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(struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
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if (argc > 1) {
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if (argv[1][0] == '0') {
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/* assert */
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printf("PMC-RESETOUT# asserted\n");
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out_8(&cpld->control,
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CPLD_CONTROL_RESETOUT_N_GATE);
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} else {
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|
/* deassert */
|
|
printf("PMC-RESETOUT# deasserted\n");
|
|
out_8(&cpld->control,
|
|
CPLD_CONTROL_RESETOUT_N |
|
|
CPLD_CONTROL_RESETOUT_N_GATE);
|
|
}
|
|
} else {
|
|
printf("PMC-RESETOUT# is %s\n",
|
|
(in_8(&cpld->control) & CPLD_CONTROL_RESETOUT_N) ?
|
|
"inactive" : "active");
|
|
}
|
|
return 0;
|
|
}
|
|
U_BOOT_CMD(
|
|
resetout, 2, 1, do_resetout,
|
|
"assert PMC-RESETOUT# signal",
|
|
""
|
|
);
|