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11d3ede42c
The UniPhier SoC family has not supported ARMv8 yet, but these would cause warnings if they were compiled with a 64bit compiler. Before adding the ARMv8 support really, fix them now. Because UniPhier SoCs do not support Large Physical Address Extension, casting "phys_addr_t" into "unsigned long" would carry the address as is. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
120 lines
3.9 KiB
C
120 lines
3.9 KiB
C
/*
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* UniPhier SG (SoC Glue) block registers
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*
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* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef ARCH_SG_REGS_H
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#define ARCH_SG_REGS_H
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/* Base Address */
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#define SG_CTRL_BASE 0x5f800000
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#define SG_DBG_BASE 0x5f900000
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/* Revision */
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#define SG_REVISION (SG_CTRL_BASE | 0x0000)
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#define SG_REVISION_TYPE_SHIFT 16
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#define SG_REVISION_TYPE_MASK (0xff << SG_REVISION_TYPE_SHIFT)
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#define SG_REVISION_MODEL_SHIFT 8
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#define SG_REVISION_MODEL_MASK (0x3 << SG_REVISION_MODEL_SHIFT)
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#define SG_REVISION_REV_SHIFT 0
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#define SG_REVISION_REV_MASK (0x1f << SG_REVISION_REV_SHIFT)
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/* Memory Configuration */
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#define SG_MEMCONF (SG_CTRL_BASE | 0x0400)
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#define SG_MEMCONF_CH0_SZ_MASK ((0x1 << 10) | (0x03 << 0))
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#define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0))
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#define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0))
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#define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0))
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#define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0))
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#define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0))
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#define SG_MEMCONF_CH0_NUM_MASK (0x1 << 8)
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#define SG_MEMCONF_CH0_NUM_1 (0x1 << 8)
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#define SG_MEMCONF_CH0_NUM_2 (0x0 << 8)
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#define SG_MEMCONF_CH1_SZ_MASK ((0x1 << 11) | (0x03 << 2))
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#define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2))
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#define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2))
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#define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2))
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#define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2))
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#define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2))
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#define SG_MEMCONF_CH1_NUM_MASK (0x1 << 9)
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#define SG_MEMCONF_CH1_NUM_1 (0x1 << 9)
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#define SG_MEMCONF_CH1_NUM_2 (0x0 << 9)
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#define SG_MEMCONF_CH2_SZ_MASK ((0x1 << 26) | (0x03 << 16))
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#define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16))
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#define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16))
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#define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16))
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#define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16))
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#define SG_MEMCONF_CH2_NUM_MASK (0x1 << 24)
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#define SG_MEMCONF_CH2_NUM_1 (0x1 << 24)
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#define SG_MEMCONF_CH2_NUM_2 (0x0 << 24)
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/* PH1-LD6b, ProXstream2 only */
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#define SG_MEMCONF_CH2_DISABLE (0x1 << 21)
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#define SG_MEMCONF_SPARSEMEM (0x1 << 4)
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/* Pin Control */
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#define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000)
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/* PH1-Pro4, PH1-Pro5 */
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#define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700)
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/* Input Enable */
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#define SG_IECTRL (SG_CTRL_BASE | 0x1d00)
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/* Pin Monitor */
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#define SG_PINMON0 (SG_DBG_BASE | 0x0100)
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#define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19)
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#define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19)
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#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A (0x2 << 19)
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#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B (0x3 << 19)
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#define SG_PINMON0_CLK_MODE_AXOSEL_MASK (0x3 << 16)
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#define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ (0x0 << 16)
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#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ (0x1 << 16)
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#define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ (0x2 << 16)
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#define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ (0x3 << 16)
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#define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT (0x0 << 16)
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#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U (0x1 << 16)
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#define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16)
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#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16)
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#ifdef __ASSEMBLY__
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.macro sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd
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ldr \ra, =(SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride)
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ldr \rd, [\ra]
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and \rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32))
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orr \rd, \rd, #(\muxval << (\pin * \mux_bits % 32))
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str \rd, [\ra]
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.endm
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#else
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#include <linux/types.h>
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#include <linux/io.h>
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static inline void sg_set_pinsel(unsigned pin, unsigned muxval,
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unsigned mux_bits, unsigned reg_stride)
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{
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unsigned shift = pin * mux_bits % 32;
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unsigned long reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride;
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u32 mask = (1U << mux_bits) - 1;
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u32 tmp;
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tmp = readl(reg);
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tmp &= ~(mask << shift);
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tmp |= (mask & muxval) << shift;
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writel(tmp, reg);
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}
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#endif /* __ASSEMBLY__ */
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#endif /* ARCH_SG_REGS_H */
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