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8034b5171f
These pin mux settings are cared by the pinctrl drivers. Remove the ad-hoc code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
35 lines
1.2 KiB
C
35 lines
1.2 KiB
C
/*
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* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/io.h>
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#include "../init.h"
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#include "../sg-regs.h"
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void ph1_sld8_pin_init(void)
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{
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/* Comment format: PAD Name -> Function Name */
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#ifdef CONFIG_NAND_DENALI
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sg_set_pinsel(15, 0, 8, 4); /* XNFRE_GB -> XNFRE_GB */
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sg_set_pinsel(16, 0, 8, 4); /* XNFWE_GB -> XNFWE_GB */
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sg_set_pinsel(17, 0, 8, 4); /* XFALE_GB -> NFALE_GB */
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sg_set_pinsel(18, 0, 8, 4); /* XFCLE_GB -> NFCLE_GB */
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sg_set_pinsel(19, 0, 8, 4); /* XNFWP_GB -> XFNWP_GB */
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sg_set_pinsel(20, 0, 8, 4); /* XNFCE0_GB -> XNFCE0_GB */
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sg_set_pinsel(21, 0, 8, 4); /* NANDRYBY0_GB -> NANDRYBY0_GB */
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sg_set_pinsel(22, 0, 8, 4); /* XFNCE1_GB -> XFNCE1_GB */
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sg_set_pinsel(23, 0, 8, 4); /* NANDRYBY1_GB -> NANDRYBY1_GB */
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sg_set_pinsel(24, 0, 8, 4); /* NFD0_GB -> NFD0_GB */
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sg_set_pinsel(25, 0, 8, 4); /* NFD1_GB -> NFD1_GB */
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sg_set_pinsel(26, 0, 8, 4); /* NFD2_GB -> NFD2_GB */
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sg_set_pinsel(27, 0, 8, 4); /* NFD3_GB -> NFD3_GB */
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sg_set_pinsel(28, 0, 8, 4); /* NFD4_GB -> NFD4_GB */
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sg_set_pinsel(29, 0, 8, 4); /* NFD5_GB -> NFD5_GB */
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sg_set_pinsel(30, 0, 8, 4); /* NFD6_GB -> NFD6_GB */
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sg_set_pinsel(31, 0, 8, 4); /* NFD7_GB -> NFD7_GB */
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#endif
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}
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