mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-29 19:02:12 +00:00
9ca71c9c19
Add basic support for the Nuvoton NPCM845 EVB (Arbel). Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
136 lines
3 KiB
Text
136 lines
3 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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#include <dt-bindings/reset/nuvoton,npcm8xx-reset.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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/* external reference clock */
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clk_refclk: clk-refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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clock-output-names = "refclk";
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};
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ahb {
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rstc: reset-controller@f0801000 {
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compatible = "nuvoton,npcm845-reset", "syscon",
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"simple-mfd";
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reg = <0x0 0xf0801000 0x0 0xC4>;
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rstc1: reset-controller1 {
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compatible = "syscon-reset";
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#reset-cells = <1>;
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regmap = <&rstc>;
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offset = <NPCM8XX_RESET_IPSRST1>;
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mask = <0xFFFFFFFF>;
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};
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rstc2: reset-controller2 {
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compatible = "syscon-reset";
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#reset-cells = <1>;
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regmap = <&rstc>;
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offset = <NPCM8XX_RESET_IPSRST2>;
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mask = <0xFFFFFFFF>;
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};
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rstc3: reset-controller3 {
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compatible = "syscon-reset";
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#reset-cells = <1>;
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regmap = <&rstc>;
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offset = <NPCM8XX_RESET_IPSRST3>;
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mask = <0xFFFFFFFF>;
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};
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rstc4: reset-controller4 {
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compatible = "syscon-reset";
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#reset-cells = <1>;
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regmap = <&rstc>;
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offset = <NPCM8XX_RESET_IPSRST4>;
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mask = <0xFFFFFFFF>;
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};
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};
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clk: clock-controller@f0801000 {
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compatible = "nuvoton,npcm845-clk", "syscon";
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#clock-cells = <1>;
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clock-controller;
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reg = <0x0 0xf0801000 0x0 0x1000>;
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clock-names = "refclk";
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clocks = <&clk_refclk>;
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};
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apb {
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serial0: serial@0 {
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compatible = "nuvoton,npcm845-uart";
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reg = <0x0 0x1000>;
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clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>;
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clock-frequency = <24000000>;
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status = "disabled";
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};
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gpio0: gpio0@10000 {
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compatible = "nuvoton,npcm-gpio";
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reg = <0x10000 0xB0>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "gpio0";
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};
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gpio1: gpio1@11000 {
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compatible = "nuvoton,npcm-gpio";
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reg = <0x11000 0xB0>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "gpio1";
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};
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gpio2: gpio2@12000 {
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compatible = "nuvoton,npcm-gpio";
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reg = <0x12000 0xB0>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "gpio2";
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};
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gpio3: gpio3@13000 {
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compatible = "nuvoton,npcm-gpio";
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reg = <0x13000 0xB0>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "gpio3";
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};
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gpio4: gpio4@14000 {
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compatible = "nuvoton,npcm-gpio";
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reg = <0x14000 0xB0>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "gpio4";
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};
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gpio5: gpio5@15000 {
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compatible = "nuvoton,npcm-gpio";
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reg = <0x15000 0xB0>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "gpio5";
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};
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gpio6: gpio6@16000 {
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compatible = "nuvoton,npcm-gpio";
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reg = <0x16000 0xB0>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "gpio6";
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};
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gpio7: gpio7@17000 {
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compatible = "nuvoton,npcm-gpio";
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reg = <0x17000 0xB0>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "gpio7";
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};
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};
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};
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};
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