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b14b0b1e7b
This patch adds the SDHCI device tree nodes to the Armada AP806 dtsi file which is used by the Armada 7k/8K SoCs. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
256 lines
6.9 KiB
Text
256 lines
6.9 KiB
Text
/*
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* Copyright (C) 2016 Marvell Technology Group Ltd.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPLv2 or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/*
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* Device Tree file for Marvell Armada AP806.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/dts-v1/;
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/ {
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model = "Marvell Armada AP806";
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compatible = "marvell,armada-ap806";
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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ap806 {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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config-space {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x0 0x0 0xf0000000 0x1000000>;
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gic: interrupt-controller@210000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupt-controller;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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reg = <0x210000 0x10000>,
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<0x220000 0x20000>,
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<0x240000 0x20000>,
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<0x260000 0x20000>;
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gic_v2m0: v2m@280000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x280000 0x1000>;
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arm,msi-base-spi = <160>;
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arm,msi-num-spis = <32>;
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};
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gic_v2m1: v2m@290000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x290000 0x1000>;
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arm,msi-base-spi = <192>;
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arm,msi-num-spis = <32>;
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};
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gic_v2m2: v2m@2a0000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x2a0000 0x1000>;
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arm,msi-base-spi = <224>;
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arm,msi-num-spis = <32>;
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};
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gic_v2m3: v2m@2b0000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x2b0000 0x1000>;
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arm,msi-base-spi = <256>;
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arm,msi-num-spis = <32>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
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};
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odmi: odmi@300000 {
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compatible = "marvell,odmi-controller";
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interrupt-controller;
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msi-controller;
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marvell,odmi-frames = <4>;
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reg = <0x300000 0x4000>,
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<0x304000 0x4000>,
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<0x308000 0x4000>,
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<0x30C000 0x4000>;
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marvell,spi-base = <128>, <136>, <144>, <152>;
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};
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ap_pinctl: ap-pinctl@6F4000 {
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compatible = "marvell,armada-ap806-pinctrl";
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bank-name ="apn-806";
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reg = <0x6F4000 0x10>;
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pin-count = <20>;
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max-func = <3>;
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ap_i2c0_pins: i2c-pins-0 {
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marvell,pins = < 4 5 >;
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marvell,function = <3>;
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};
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ap_emmc_pins: emmc-pins-0 {
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marvell,pins = < 0 1 2 3 4 5 6 7
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8 9 10 >;
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marvell,function = <1>;
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};
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};
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xor@400000 {
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compatible = "marvell,mv-xor-v2";
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reg = <0x400000 0x1000>,
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<0x410000 0x1000>;
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msi-parent = <&gic_v2m0>;
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dma-coherent;
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};
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xor@420000 {
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compatible = "marvell,mv-xor-v2";
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reg = <0x420000 0x1000>,
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<0x430000 0x1000>;
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msi-parent = <&gic_v2m0>;
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dma-coherent;
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};
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xor@440000 {
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compatible = "marvell,mv-xor-v2";
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reg = <0x440000 0x1000>,
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<0x450000 0x1000>;
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msi-parent = <&gic_v2m0>;
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dma-coherent;
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};
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xor@460000 {
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compatible = "marvell,mv-xor-v2";
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reg = <0x460000 0x1000>,
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<0x470000 0x1000>;
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msi-parent = <&gic_v2m0>;
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dma-coherent;
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};
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spi0: spi@510600 {
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compatible = "marvell,armada-380-spi";
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reg = <0x510600 0x50>;
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ap_syscon 3>;
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status = "disabled";
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};
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i2c0: i2c@511000 {
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compatible = "marvell,mv78230-i2c";
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reg = <0x511000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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timeout-ms = <1000>;
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clocks = <&ap_syscon 3>;
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status = "disabled";
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};
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uart0: serial@512000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x512000 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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clocks = <&ap_syscon 3>;
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status = "disabled";
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clock-frequency = <200000000>;
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};
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uart1: serial@512100 {
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compatible = "snps,dw-apb-uart";
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reg = <0x512100 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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clocks = <&ap_syscon 3>;
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status = "disabled";
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};
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ap_sdhci0: sdhci@6e0000 {
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compatible = "marvell,armada-8k-sdhci";
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reg = <0x6e0000 0x300>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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dma-coherent;
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status = "disabled";
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};
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ap_syscon: system-controller@6f4000 {
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compatible = "marvell,ap806-system-controller",
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"syscon";
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#clock-cells = <1>;
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clock-output-names = "ap-cpu-cluster-0",
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"ap-cpu-cluster-1",
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"ap-fixed", "ap-mss";
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reg = <0x6f4000 0x1000>;
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};
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};
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};
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};
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