mirror of
https://github.com/AsahiLinux/u-boot
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12ca05a38b
This is not really a config. Rename it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
331 lines
9.9 KiB
C
331 lines
9.9 KiB
C
/*
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* Common configuration options for ifm camera boards
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*
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* (C) Copyright 2005
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* Sebastien Cazaux, ifm electronic gmbh
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*
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* (C) Copyright 2012
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* DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __O2D_CONFIG_H
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#define __O2D_CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_MPC5200
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#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* running at 33.000000MHz */
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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/* log base 2 of the above value */
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#define CONFIG_SYS_CACHELINE_SHIFT 5
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#endif
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/*
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#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
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CONFIG_SYS_POST_I2C)
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*/
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#ifdef CONFIG_POST
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/* preserve space for the post_word at end of on-chip SRAM */
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#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
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#endif
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/*
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* Serial console configuration
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*/
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#define CONFIG_PSC_CONSOLE 5 /* console is on PSC5 */
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#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{ 9600, 19200, 38400, 57600, 115200, 230400 }
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/*
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* PCI Mapping:
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* 0x40000000 - 0x4fffffff - PCI Memory
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* 0x50000000 - 0x50ffffff - PCI IO Space
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*/
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#undef CONFIG_PCI
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#define CONFIG_PCI_PNP 1
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#define CONFIG_PCI_MEM_BUS 0x40000000
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#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
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#define CONFIG_PCI_MEM_SIZE 0x10000000
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#define CONFIG_PCI_IO_BUS 0x50000000
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#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
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#define CONFIG_PCI_IO_SIZE 0x01000000
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#define CONFIG_SYS_XLB_PIPELINING 1
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/* Partitions */
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_ISO_PARTITION
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#define CONFIG_TIMESTAMP /* Print image info with timestamp */
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#define CONFIG_SYS_ALT_MEMTEST /* Much more complex memory test */
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/*
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* Supported commands
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*/
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#define CONFIG_CMD_EEPROM
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#ifdef CONFIG_PCI
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#define CONFIG_CMD_PCI
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#endif
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#ifdef CONFIG_POST
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#define CONFIG_CMD_DIAG
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#endif
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#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) || (CONFIG_SYS_TEXT_BASE == 0xFF000000)
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/* Boot low with 16 or 32 MB Flash */
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#define CONFIG_SYS_LOWBOOT 1
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#elif (CONFIG_SYS_TEXT_BASE != 0x00100000)
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#error "CONFIG_SYS_TEXT_BASE value is invalid"
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#endif
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#define CONFIG_PREBOOT "run master"
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#undef CONFIG_BOOTARGS
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#if !defined(CONSOLE_DEV)
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#define CONSOLE_DEV "ttyPSC1"
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#endif
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/*
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* Default environment for booting old and new kernel versions
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*/
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#define CONFIG_IFM_DEFAULT_ENV_OLD \
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"flash_self_old=run ramargs addip addmem;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"flash_nfs_old=run nfsargs addip addmem;" \
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"bootm ${kernel_addr}\0" \
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"net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \
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"run nfsargs addip addmem;" \
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"bootm ${kernel_addr_r}\0"
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#define CONFIG_IFM_DEFAULT_ENV_NEW \
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"fdt_addr_r=900000\0" \
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"fdt_file="CONFIG_BOARD_NAME"/"CONFIG_BOARD_NAME".dtb\0" \
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"flash_self=run ramargs addip addtty addmisc;" \
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"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
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"flash_nfs=run nfsargs addip addtty addmisc;" \
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"bootm ${kernel_addr} - ${fdt_addr}\0" \
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"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
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"tftp ${fdt_addr_r} ${fdt_file}; " \
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"run nfsargs addip addtty addmisc;" \
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"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
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#define CONFIG_IFM_DEFAULT_ENV_SETTINGS \
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"IOpin=0x64\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addmem=setenv bootargs ${bootargs} ${memlimit}\0" \
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"addmisc=sete bootargs ${bootargs} ${miscargs}\0" \
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"addtty=sete bootargs ${bootargs} console=" \
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CONSOLE_DEV ",${baudrate}\0" \
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"bootfile="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0" \
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"kernel_addr_r=600000\0" \
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"initrd_high=0x03e00000\0" \
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"memlimit=mem="CONFIG_BOARD_MEM_LIMIT"M\0" \
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"memtest=mtest 0x00100000 "__stringify(CONFIG_SYS_MEMTEST_END)" 0 1\0" \
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"netdev=eth0\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"linuxname="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0"\
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"progLinux=tftp 200000 ${linuxname};erase ${linbot} ${lintop};" \
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"cp.b ${fileaddr} ${linbot} ${filesize}\0" \
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"ramname="CONFIG_BOARD_NAME"/uRamdisk_"CONFIG_BOARD_NAME"_act\0"\
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"progRam=tftp 200000 ${ramname};erase ${rambot} ${ramtop};" \
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"cp.b ${fileaddr} ${rambot} ${filesize}\0" \
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"jffname="CONFIG_BOARD_NAME"/uJFFS2_"CONFIG_BOARD_NAME"_act\0" \
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"progJff=tftp 200000 ${jffname};erase ${jffbot} ${jfftop};" \
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"cp.b ${fileaddr} ${jffbot} ${filesize}\0" \
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"rootpath=/opt/eldk/ppc_6xx\0" \
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"uboname=" CONFIG_BOARD_NAME \
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"/u-boot.bin_" CONFIG_BOARD_NAME "_act\0" \
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"progubo=tftp 200000 ${uboname};" \
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"protect off ${ubobot} ${ubotop};" \
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"erase ${ubobot} ${ubotop};" \
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"cp.b ${fileaddr} ${ubobot} ${filesize}\0" \
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"unlock=yes\0" \
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"post=echo !!! "CONFIG_BOARD_NAME" POWER ON SELF TEST !!!;" \
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"setenv bootdelay 1;" \
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"crc32 "__stringify(CONFIG_SYS_TEXT_BASE)" " \
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BOARD_POST_CRC32_END";" \
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"setenv bootcmd "CONFIG_BOARD_BOOTCMD";saveenv;reset\0"
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#define CONFIG_BOOTCOMMAND "run post"
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/*
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* IPB Bus clocking configuration.
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*/
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#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
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#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
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/*
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* PCI Bus clocking configuration
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*
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* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
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* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
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* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
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*/
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#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
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#endif
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/*
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* I2C configuration
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*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */
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#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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/*
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* EEPROM configuration:
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*
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* O2DNT board is equiped with Ramtron FRAM device FM24CL16
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* 16 Kib Ferroelectric Nonvolatile serial RAM memory
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* organized as 2048 x 8 bits and addressable as eight I2C devices
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* 0x50 ... 0x57 each 256 bytes in size
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*
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*/
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#define CONFIG_SYS_I2C_FRAM
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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/*
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* There is no write delay with FRAM, write operations are performed at bus
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* speed. Thus, no status polling or write delay is needed.
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*/
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/*
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* Flash configuration
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*/
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#define CONFIG_SYS_FLASH_CFI 1
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define CONFIG_FLASH_16BIT
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#define CONFIG_SYS_FLASH_CFI_AMD_RESET
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Erase Timeout (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (in ms) */
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/* Timeout for Flash Clear Lock Bits (in ms) */
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#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000
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/* "Real" (hardware) sectors protection */
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#define CONFIG_SYS_FLASH_PROTECTION
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/*
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* Environment settings
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_SIZE 0x20000
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_OVERWRITE 1
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
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/*
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* Memory map
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*/
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#define CONFIG_SYS_MBAR 0xF0000000
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
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/* Use SRAM until RAM will be available */
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#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
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#ifdef CONFIG_POST
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/* preserve space for the post_word at end of on-chip SRAM */
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#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
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#else
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/* End of used area in DPRAM */
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#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
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#endif
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* 192 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* 128 kB for malloc() */
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial map for Linux */
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_RAMBOOT 1
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#endif
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/*
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* Ethernet configuration
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*/
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#define CONFIG_MPC5xxx_FEC
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#define CONFIG_MPC5xxx_FEC_MII100
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#define CONFIG_PHY_ADDR 0x00
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#define CONFIG_RESET_PHY_R
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/*
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* GPIO configuration
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*/
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#define CONFIG_SYS_GPIO_DATADIR 0x00000064 /* PSC1_2, PSC2_1,2 output */
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#define CONFIG_SYS_GPIO_OPENDRAIN 0x00000000 /* No open drain */
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#define CONFIG_SYS_GPIO_DATAVALUE 0x00000000 /* PSC1_1 to 1, rest to 0 */
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#define CONFIG_SYS_GPIO_ENABLE 0x00000064 /* PSC1_2, PSC2_1,2 enable */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_CMDLINE_EDITING
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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/* max number of command args */
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#define CONFIG_SYS_MAXARGS 16
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/* default load address */
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#define CONFIG_SYS_LOAD_ADDR 0x100000
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/* decrementer freq: 1 ms ticks */
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/*
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* Various low-level settings
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*/
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#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
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#define CONFIG_SYS_HID0_FINAL HID0_ICE
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#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
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#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
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#define CONFIG_BOARD_EARLY_INIT_R
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#define CONFIG_SYS_CS_BURST 0x00000000
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#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
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/*
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* DT support
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*/
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#define OF_CPU "PowerPC,5200@0"
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#define OF_SOC "soc5200@f0000000"
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#define OF_TBCLK (bd->bi_busfreq / 4)
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#endif /* __O2D_CONFIG_H */
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