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340848b185
Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform. Tested on LS1021AQDS, LS1021ATWR. Test CPU hotplug times: 60K Test kernel boot times: 1.2K Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
126 lines
2.1 KiB
ArmAsm
126 lines
2.1 KiB
ArmAsm
/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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* Author: Wang Dongsheng <dongsheng.wang@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/armv7.h>
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#include <asm/arch-armv7/generictimer.h>
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#include <asm/psci.h>
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#define SCFG_CORE0_SFT_RST 0x130
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#define SCFG_CORESRENCR 0x204
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#define DCFG_CCSR_BRR 0x0E4
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#define DCFG_CCSR_SCRATCHRW1 0x200
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.pushsection ._secure.text, "ax"
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.arch_extension sec
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#define ONE_MS (GENERIC_TIMER_CLK / 1000)
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#define RESET_WAIT (30 * ONE_MS)
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@ r1 = target CPU
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@ r2 = target PC
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.globl psci_cpu_on
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psci_cpu_on:
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push {lr}
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@ Clear and Get the correct CPU number
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@ r1 = 0xf01
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and r1, r1, #0xff
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mov r0, r1
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bl psci_get_cpu_stack_top
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str r2, [r0]
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dsb
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@ Get DCFG base address
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movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
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movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
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@ Detect target CPU state
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ldr r2, [r4, #DCFG_CCSR_BRR]
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rev r2, r2
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lsr r2, r2, r1
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ands r2, r2, #1
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beq holdoff_release
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@ Reset target CPU
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@ Get SCFG base address
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movw r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff)
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movt r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16)
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@ Enable CORE Soft Reset
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movw r5, #0
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movt r5, #(1 << 15)
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rev r5, r5
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str r5, [r0, #SCFG_CORESRENCR]
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@ Get CPUx offset register
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mov r6, #0x4
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mul r6, r6, r1
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add r2, r0, r6
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@ Do reset on target CPU
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movw r5, #0
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movt r5, #(1 << 15)
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rev r5, r5
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str r5, [r2, #SCFG_CORE0_SFT_RST]
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@ Wait target CPU up
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timer_wait r2, RESET_WAIT
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@ Disable CORE soft reset
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mov r5, #0
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str r5, [r0, #SCFG_CORESRENCR]
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holdoff_release:
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@ Release on target CPU
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ldr r2, [r4, #DCFG_CCSR_BRR]
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mov r6, #1
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lsl r6, r6, r1 @ 32 bytes per CPU
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rev r6, r6
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orr r2, r2, r6
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str r2, [r4, #DCFG_CCSR_BRR]
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@ Set secondary boot entry
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ldr r6, =psci_cpu_entry
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rev r6, r6
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str r6, [r4, #DCFG_CCSR_SCRATCHRW1]
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isb
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dsb
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@ Return
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mov r0, #ARM_PSCI_RET_SUCCESS
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pop {lr}
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bx lr
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.globl psci_cpu_off
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psci_cpu_off:
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bl psci_cpu_off_common
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1: wfi
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b 1b
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.globl psci_arch_init
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psci_arch_init:
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mov r6, lr
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bl psci_get_cpu_id
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bl psci_get_cpu_stack_top
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mov sp, r0
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bx r6
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.globl psci_text_end
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psci_text_end:
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.popsection
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