mirror of
https://github.com/AsahiLinux/u-boot
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cd93d625fd
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
316 lines
10 KiB
C
316 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2017, Impinj, Inc.
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*/
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#include <log.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <common.h>
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#include <dm.h>
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#include <dt-bindings/reset/imx7-reset.h>
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#include <dt-bindings/reset/imx8mq-reset.h>
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#include <reset-uclass.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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struct imx7_reset_priv {
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void __iomem *base;
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struct reset_ops ops;
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};
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struct imx7_src_signal {
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unsigned int offset, bit;
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};
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enum imx7_src_registers {
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SRC_A7RCR0 = 0x0004,
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SRC_M4RCR = 0x000c,
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SRC_ERCR = 0x0014,
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SRC_HSICPHY_RCR = 0x001c,
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SRC_USBOPHY1_RCR = 0x0020,
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SRC_USBOPHY2_RCR = 0x0024,
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SRC_MIPIPHY_RCR = 0x0028,
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SRC_PCIEPHY_RCR = 0x002c,
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SRC_DDRC_RCR = 0x1000,
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};
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static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = {
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[IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) },
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[IMX7_RESET_A7_CORE_POR_RESET1] = { SRC_A7RCR0, BIT(1) },
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[IMX7_RESET_A7_CORE_RESET0] = { SRC_A7RCR0, BIT(4) },
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[IMX7_RESET_A7_CORE_RESET1] = { SRC_A7RCR0, BIT(5) },
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[IMX7_RESET_A7_DBG_RESET0] = { SRC_A7RCR0, BIT(8) },
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[IMX7_RESET_A7_DBG_RESET1] = { SRC_A7RCR0, BIT(9) },
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[IMX7_RESET_A7_ETM_RESET0] = { SRC_A7RCR0, BIT(12) },
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[IMX7_RESET_A7_ETM_RESET1] = { SRC_A7RCR0, BIT(13) },
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[IMX7_RESET_A7_SOC_DBG_RESET] = { SRC_A7RCR0, BIT(20) },
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[IMX7_RESET_A7_L2RESET] = { SRC_A7RCR0, BIT(21) },
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[IMX7_RESET_SW_M4C_RST] = { SRC_M4RCR, BIT(1) },
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[IMX7_RESET_SW_M4P_RST] = { SRC_M4RCR, BIT(2) },
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[IMX7_RESET_EIM_RST] = { SRC_ERCR, BIT(0) },
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[IMX7_RESET_HSICPHY_PORT_RST] = { SRC_HSICPHY_RCR, BIT(1) },
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[IMX7_RESET_USBPHY1_POR] = { SRC_USBOPHY1_RCR, BIT(0) },
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[IMX7_RESET_USBPHY1_PORT_RST] = { SRC_USBOPHY1_RCR, BIT(1) },
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[IMX7_RESET_USBPHY2_POR] = { SRC_USBOPHY2_RCR, BIT(0) },
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[IMX7_RESET_USBPHY2_PORT_RST] = { SRC_USBOPHY2_RCR, BIT(1) },
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[IMX7_RESET_MIPI_PHY_MRST] = { SRC_MIPIPHY_RCR, BIT(1) },
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[IMX7_RESET_MIPI_PHY_SRST] = { SRC_MIPIPHY_RCR, BIT(2) },
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[IMX7_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) | BIT(1) },
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[IMX7_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
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[IMX7_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
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[IMX7_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
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[IMX7_RESET_DDRC_PRST] = { SRC_DDRC_RCR, BIT(0) },
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[IMX7_RESET_DDRC_CORE_RST] = { SRC_DDRC_RCR, BIT(1) },
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};
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static int imx7_reset_deassert_imx7(struct reset_ctl *rst)
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{
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struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
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const struct imx7_src_signal *sig = imx7_src_signals;
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u32 val;
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if (rst->id >= IMX7_RESET_NUM)
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return -EINVAL;
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if (rst->id == IMX7_RESET_PCIEPHY) {
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/*
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* wait for more than 10us to release phy g_rst and
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* btnrst
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*/
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udelay(10);
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}
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val = readl(priv->base + sig[rst->id].offset);
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switch (rst->id) {
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case IMX7_RESET_PCIE_CTRL_APPS_EN:
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val |= sig[rst->id].bit;
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break;
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default:
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val &= ~sig[rst->id].bit;
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break;
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}
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writel(val, priv->base + sig[rst->id].offset);
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return 0;
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}
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static int imx7_reset_assert_imx7(struct reset_ctl *rst)
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{
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struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
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const struct imx7_src_signal *sig = imx7_src_signals;
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u32 val;
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if (rst->id >= IMX7_RESET_NUM)
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return -EINVAL;
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val = readl(priv->base + sig[rst->id].offset);
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switch (rst->id) {
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case IMX7_RESET_PCIE_CTRL_APPS_EN:
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val &= ~sig[rst->id].bit;
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break;
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default:
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val |= sig[rst->id].bit;
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break;
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}
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writel(val, priv->base + sig[rst->id].offset);
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return 0;
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}
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enum imx8mq_src_registers {
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SRC_A53RCR0 = 0x0004,
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SRC_HDMI_RCR = 0x0030,
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SRC_DISP_RCR = 0x0034,
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SRC_GPU_RCR = 0x0040,
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SRC_VPU_RCR = 0x0044,
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SRC_PCIE2_RCR = 0x0048,
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SRC_MIPIPHY1_RCR = 0x004c,
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SRC_MIPIPHY2_RCR = 0x0050,
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SRC_DDRC2_RCR = 0x1004,
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};
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static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = {
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[IMX8MQ_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) },
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[IMX8MQ_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) },
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[IMX8MQ_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) },
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[IMX8MQ_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) },
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[IMX8MQ_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) },
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[IMX8MQ_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) },
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[IMX8MQ_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) },
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[IMX8MQ_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) },
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[IMX8MQ_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) },
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[IMX8MQ_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) },
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[IMX8MQ_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) },
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[IMX8MQ_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) },
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[IMX8MQ_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) },
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[IMX8MQ_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) },
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[IMX8MQ_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) },
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[IMX8MQ_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) },
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[IMX8MQ_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) },
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[IMX8MQ_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) },
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[IMX8MQ_RESET_SW_NON_SCLR_M4C_RST] = { SRC_M4RCR, BIT(0) },
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[IMX8MQ_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) },
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[IMX8MQ_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) },
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[IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N] = { SRC_MIPIPHY_RCR, BIT(1) },
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[IMX8MQ_RESET_MIPI_DSI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(2) },
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[IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(3) },
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[IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N] = { SRC_MIPIPHY_RCR, BIT(4) },
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[IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N] = { SRC_MIPIPHY_RCR, BIT(5) },
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[IMX8MQ_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR,
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BIT(2) | BIT(1) },
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[IMX8MQ_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
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[IMX8MQ_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
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[IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
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[IMX8MQ_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) },
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[IMX8MQ_RESET_DISP_RESET] = { SRC_DISP_RCR, BIT(0) },
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[IMX8MQ_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) },
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[IMX8MQ_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) },
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[IMX8MQ_RESET_PCIEPHY2] = { SRC_PCIE2_RCR,
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BIT(2) | BIT(1) },
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[IMX8MQ_RESET_PCIEPHY2_PERST] = { SRC_PCIE2_RCR, BIT(3) },
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[IMX8MQ_RESET_PCIE2_CTRL_APPS_EN] = { SRC_PCIE2_RCR, BIT(6) },
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[IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF] = { SRC_PCIE2_RCR, BIT(11) },
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[IMX8MQ_RESET_MIPI_CSI1_CORE_RESET] = { SRC_MIPIPHY1_RCR, BIT(0) },
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[IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET] = { SRC_MIPIPHY1_RCR, BIT(1) },
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[IMX8MQ_RESET_MIPI_CSI1_ESC_RESET] = { SRC_MIPIPHY1_RCR, BIT(2) },
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[IMX8MQ_RESET_MIPI_CSI2_CORE_RESET] = { SRC_MIPIPHY2_RCR, BIT(0) },
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[IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET] = { SRC_MIPIPHY2_RCR, BIT(1) },
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[IMX8MQ_RESET_MIPI_CSI2_ESC_RESET] = { SRC_MIPIPHY2_RCR, BIT(2) },
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[IMX8MQ_RESET_DDRC1_PRST] = { SRC_DDRC_RCR, BIT(0) },
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[IMX8MQ_RESET_DDRC1_CORE_RESET] = { SRC_DDRC_RCR, BIT(1) },
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[IMX8MQ_RESET_DDRC1_PHY_RESET] = { SRC_DDRC_RCR, BIT(2) },
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[IMX8MQ_RESET_DDRC2_PHY_RESET] = { SRC_DDRC2_RCR, BIT(0) },
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[IMX8MQ_RESET_DDRC2_CORE_RESET] = { SRC_DDRC2_RCR, BIT(1) },
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[IMX8MQ_RESET_DDRC2_PRST] = { SRC_DDRC2_RCR, BIT(2) },
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};
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static int imx7_reset_deassert_imx8mq(struct reset_ctl *rst)
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{
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struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
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const struct imx7_src_signal *sig = imx8mq_src_signals;
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u32 val;
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if (rst->id >= IMX8MQ_RESET_NUM)
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return -EINVAL;
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if (rst->id == IMX8MQ_RESET_PCIEPHY ||
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rst->id == IMX8MQ_RESET_PCIEPHY2) {
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/*
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* wait for more than 10us to release phy g_rst and
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* btnrst
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*/
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udelay(10);
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}
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val = readl(priv->base + sig[rst->id].offset);
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switch (rst->id) {
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case IMX8MQ_RESET_PCIE_CTRL_APPS_EN:
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case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN: /* fallthrough */
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case IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N: /* fallthrough */
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case IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N: /* fallthrough */
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case IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N: /* fallthrough */
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case IMX8MQ_RESET_MIPI_DSI_RESET_N: /* fallthrough */
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case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N: /* fallthrough */
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val |= sig[rst->id].bit;
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break;
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default:
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val &= ~sig[rst->id].bit;
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break;
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}
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writel(val, priv->base + sig[rst->id].offset);
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return 0;
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}
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static int imx7_reset_assert_imx8mq(struct reset_ctl *rst)
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{
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struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
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const struct imx7_src_signal *sig = imx8mq_src_signals;
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u32 val;
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if (rst->id >= IMX8MQ_RESET_NUM)
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return -EINVAL;
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val = readl(priv->base + sig[rst->id].offset);
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switch (rst->id) {
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case IMX8MQ_RESET_PCIE_CTRL_APPS_EN:
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case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN: /* fallthrough */
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case IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N: /* fallthrough */
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case IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N: /* fallthrough */
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case IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N: /* fallthrough */
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case IMX8MQ_RESET_MIPI_DSI_RESET_N: /* fallthrough */
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case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N: /* fallthrough */
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val &= ~sig[rst->id].bit;
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break;
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default:
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val |= sig[rst->id].bit;
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break;
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}
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writel(val, priv->base + sig[rst->id].offset);
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return 0;
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}
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static int imx7_reset_assert(struct reset_ctl *rst)
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{
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struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
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return priv->ops.rst_assert(rst);
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}
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static int imx7_reset_deassert(struct reset_ctl *rst)
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{
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struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
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return priv->ops.rst_deassert(rst);
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}
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static int imx7_reset_free(struct reset_ctl *rst)
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{
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return 0;
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}
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static int imx7_reset_request(struct reset_ctl *rst)
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{
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return 0;
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}
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static const struct reset_ops imx7_reset_reset_ops = {
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.request = imx7_reset_request,
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.rfree = imx7_reset_free,
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.rst_assert = imx7_reset_assert,
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.rst_deassert = imx7_reset_deassert,
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};
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static const struct udevice_id imx7_reset_ids[] = {
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{ .compatible = "fsl,imx7d-src" },
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{ .compatible = "fsl,imx8mq-src" },
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{ }
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};
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static int imx7_reset_probe(struct udevice *dev)
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{
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struct imx7_reset_priv *priv = dev_get_priv(dev);
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priv->base = dev_remap_addr(dev);
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if (!priv->base)
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return -ENOMEM;
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if (device_is_compatible(dev, "fsl,imx8mq-src")) {
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priv->ops.rst_assert = imx7_reset_assert_imx8mq;
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priv->ops.rst_deassert = imx7_reset_deassert_imx8mq;
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} else if (device_is_compatible(dev, "fsl,imx7d-src")) {
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priv->ops.rst_assert = imx7_reset_assert_imx7;
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priv->ops.rst_deassert = imx7_reset_deassert_imx7;
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}
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return 0;
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}
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U_BOOT_DRIVER(imx7_reset) = {
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.name = "imx7_reset",
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.id = UCLASS_RESET,
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.of_match = imx7_reset_ids,
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.ops = &imx7_reset_reset_ops,
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.probe = imx7_reset_probe,
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.priv_auto_alloc_size = sizeof(struct imx7_reset_priv),
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};
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