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90526e9fba
Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
620 lines
15 KiB
C
620 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Freescale i.MX28 APBH DMA driver
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* Based on code from LTIB:
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* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2017 NXP
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*
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*/
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#include <cpu_func.h>
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#include <asm/cache.h>
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#include <linux/list.h>
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#include <common.h>
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#include <malloc.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/dma.h>
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#include <asm/mach-imx/regs-apbh.h>
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static struct mxs_dma_chan mxs_dma_channels[MXS_MAX_DMA_CHANNELS];
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/*
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* Test is the DMA channel is valid channel
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*/
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int mxs_dma_validate_chan(int channel)
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{
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struct mxs_dma_chan *pchan;
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if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS))
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return -EINVAL;
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pchan = mxs_dma_channels + channel;
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if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))
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return -EINVAL;
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return 0;
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}
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/*
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* Return the address of the command within a descriptor.
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*/
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static unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc)
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{
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return desc->address + offsetof(struct mxs_dma_desc, cmd);
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}
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/*
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* Read a DMA channel's hardware semaphore.
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*
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* As used by the MXS platform's DMA software, the DMA channel's hardware
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* semaphore reflects the number of DMA commands the hardware will process, but
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* has not yet finished. This is a volatile value read directly from hardware,
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* so it must be be viewed as immediately stale.
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*
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* If the channel is not marked busy, or has finished processing all its
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* commands, this value should be zero.
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*
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* See mxs_dma_append() for details on how DMA command blocks must be configured
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* to maintain the expected behavior of the semaphore's value.
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*/
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static int mxs_dma_read_semaphore(int channel)
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{
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struct mxs_apbh_regs *apbh_regs =
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(struct mxs_apbh_regs *)MXS_APBH_BASE;
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uint32_t tmp;
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int ret;
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ret = mxs_dma_validate_chan(channel);
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if (ret)
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return ret;
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tmp = readl(&apbh_regs->ch[channel].hw_apbh_ch_sema);
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tmp &= APBH_CHn_SEMA_PHORE_MASK;
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tmp >>= APBH_CHn_SEMA_PHORE_OFFSET;
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return tmp;
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}
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#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
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void mxs_dma_flush_desc(struct mxs_dma_desc *desc)
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{
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uint32_t addr;
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uint32_t size;
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addr = (uintptr_t)desc;
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size = roundup(sizeof(struct mxs_dma_desc), MXS_DMA_ALIGNMENT);
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flush_dcache_range(addr, addr + size);
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}
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#else
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inline void mxs_dma_flush_desc(struct mxs_dma_desc *desc) {}
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#endif
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/*
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* Enable a DMA channel.
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*
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* If the given channel has any DMA descriptors on its active list, this
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* function causes the DMA hardware to begin processing them.
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*
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* This function marks the DMA channel as "busy," whether or not there are any
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* descriptors to process.
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*/
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static int mxs_dma_enable(int channel)
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{
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struct mxs_apbh_regs *apbh_regs =
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(struct mxs_apbh_regs *)MXS_APBH_BASE;
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unsigned int sem;
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struct mxs_dma_chan *pchan;
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struct mxs_dma_desc *pdesc;
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int ret;
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ret = mxs_dma_validate_chan(channel);
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if (ret)
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return ret;
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pchan = mxs_dma_channels + channel;
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if (pchan->pending_num == 0) {
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pchan->flags |= MXS_DMA_FLAGS_BUSY;
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return 0;
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}
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pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node);
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if (pdesc == NULL)
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return -EFAULT;
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if (pchan->flags & MXS_DMA_FLAGS_BUSY) {
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if (!(pdesc->cmd.data & MXS_DMA_DESC_CHAIN))
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return 0;
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sem = mxs_dma_read_semaphore(channel);
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if (sem == 0)
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return 0;
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if (sem == 1) {
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pdesc = list_entry(pdesc->node.next,
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struct mxs_dma_desc, node);
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writel(mxs_dma_cmd_address(pdesc),
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&apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar);
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}
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writel(pchan->pending_num,
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&apbh_regs->ch[channel].hw_apbh_ch_sema);
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pchan->active_num += pchan->pending_num;
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pchan->pending_num = 0;
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} else {
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pchan->active_num += pchan->pending_num;
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pchan->pending_num = 0;
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writel(mxs_dma_cmd_address(pdesc),
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&apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar);
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writel(pchan->active_num,
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&apbh_regs->ch[channel].hw_apbh_ch_sema);
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writel(1 << (channel + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),
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&apbh_regs->hw_apbh_ctrl0_clr);
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}
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pchan->flags |= MXS_DMA_FLAGS_BUSY;
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return 0;
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}
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/*
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* Disable a DMA channel.
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*
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* This function shuts down a DMA channel and marks it as "not busy." Any
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* descriptors on the active list are immediately moved to the head of the
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* "done" list, whether or not they have actually been processed by the
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* hardware. The "ready" flags of these descriptors are NOT cleared, so they
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* still appear to be active.
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*
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* This function immediately shuts down a DMA channel's hardware, aborting any
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* I/O that may be in progress, potentially leaving I/O hardware in an undefined
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* state. It is unwise to call this function if there is ANY chance the hardware
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* is still processing a command.
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*/
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static int mxs_dma_disable(int channel)
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{
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struct mxs_dma_chan *pchan;
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struct mxs_apbh_regs *apbh_regs =
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(struct mxs_apbh_regs *)MXS_APBH_BASE;
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int ret;
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ret = mxs_dma_validate_chan(channel);
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if (ret)
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return ret;
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pchan = mxs_dma_channels + channel;
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if (!(pchan->flags & MXS_DMA_FLAGS_BUSY))
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return -EINVAL;
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writel(1 << (channel + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),
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&apbh_regs->hw_apbh_ctrl0_set);
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pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
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pchan->active_num = 0;
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pchan->pending_num = 0;
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list_splice_init(&pchan->active, &pchan->done);
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return 0;
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}
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/*
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* Resets the DMA channel hardware.
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*/
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static int mxs_dma_reset(int channel)
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{
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struct mxs_apbh_regs *apbh_regs =
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(struct mxs_apbh_regs *)MXS_APBH_BASE;
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int ret;
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#if defined(CONFIG_MX23)
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uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set);
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uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET;
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#elif defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
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defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
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u32 setreg = (uintptr_t)(&apbh_regs->hw_apbh_channel_ctrl_set);
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u32 offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET;
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#endif
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ret = mxs_dma_validate_chan(channel);
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if (ret)
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return ret;
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writel(1 << (channel + offset), (uintptr_t)setreg);
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return 0;
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}
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/*
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* Enable or disable DMA interrupt.
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*
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* This function enables the given DMA channel to interrupt the CPU.
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*/
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static int mxs_dma_enable_irq(int channel, int enable)
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{
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struct mxs_apbh_regs *apbh_regs =
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(struct mxs_apbh_regs *)MXS_APBH_BASE;
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int ret;
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ret = mxs_dma_validate_chan(channel);
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if (ret)
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return ret;
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if (enable)
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writel(1 << (channel + APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET),
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&apbh_regs->hw_apbh_ctrl1_set);
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else
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writel(1 << (channel + APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET),
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&apbh_regs->hw_apbh_ctrl1_clr);
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return 0;
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}
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/*
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* Clear DMA interrupt.
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*
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* The software that is using the DMA channel must register to receive its
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* interrupts and, when they arrive, must call this function to clear them.
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*/
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static int mxs_dma_ack_irq(int channel)
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{
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struct mxs_apbh_regs *apbh_regs =
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(struct mxs_apbh_regs *)MXS_APBH_BASE;
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int ret;
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ret = mxs_dma_validate_chan(channel);
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if (ret)
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return ret;
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writel(1 << channel, &apbh_regs->hw_apbh_ctrl1_clr);
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writel(1 << channel, &apbh_regs->hw_apbh_ctrl2_clr);
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return 0;
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}
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/*
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* Request to reserve a DMA channel
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*/
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static int mxs_dma_request(int channel)
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{
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struct mxs_dma_chan *pchan;
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if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS))
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return -EINVAL;
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pchan = mxs_dma_channels + channel;
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if ((pchan->flags & MXS_DMA_FLAGS_VALID) != MXS_DMA_FLAGS_VALID)
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return -ENODEV;
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if (pchan->flags & MXS_DMA_FLAGS_ALLOCATED)
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return -EBUSY;
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pchan->flags |= MXS_DMA_FLAGS_ALLOCATED;
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pchan->active_num = 0;
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pchan->pending_num = 0;
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INIT_LIST_HEAD(&pchan->active);
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INIT_LIST_HEAD(&pchan->done);
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return 0;
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}
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/*
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* Release a DMA channel.
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*
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* This function releases a DMA channel from its current owner.
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*
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* The channel will NOT be released if it's marked "busy" (see
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* mxs_dma_enable()).
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*/
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int mxs_dma_release(int channel)
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{
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struct mxs_dma_chan *pchan;
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int ret;
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ret = mxs_dma_validate_chan(channel);
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if (ret)
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return ret;
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pchan = mxs_dma_channels + channel;
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if (pchan->flags & MXS_DMA_FLAGS_BUSY)
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return -EBUSY;
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pchan->dev = 0;
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pchan->active_num = 0;
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pchan->pending_num = 0;
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pchan->flags &= ~MXS_DMA_FLAGS_ALLOCATED;
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return 0;
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}
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/*
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* Allocate DMA descriptor
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*/
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struct mxs_dma_desc *mxs_dma_desc_alloc(void)
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{
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struct mxs_dma_desc *pdesc;
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uint32_t size;
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size = roundup(sizeof(struct mxs_dma_desc), MXS_DMA_ALIGNMENT);
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pdesc = memalign(MXS_DMA_ALIGNMENT, size);
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if (pdesc == NULL)
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return NULL;
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memset(pdesc, 0, sizeof(*pdesc));
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pdesc->address = (dma_addr_t)pdesc;
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return pdesc;
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};
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/*
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* Free DMA descriptor
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*/
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void mxs_dma_desc_free(struct mxs_dma_desc *pdesc)
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{
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if (pdesc == NULL)
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return;
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free(pdesc);
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}
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/*
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* Add a DMA descriptor to a channel.
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*
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* If the descriptor list for this channel is not empty, this function sets the
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* CHAIN bit and the NEXTCMD_ADDR fields in the last descriptor's DMA command so
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* it will chain to the new descriptor's command.
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*
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* Then, this function marks the new descriptor as "ready," adds it to the end
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* of the active descriptor list, and increments the count of pending
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* descriptors.
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*
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* The MXS platform DMA software imposes some rules on DMA commands to maintain
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* important invariants. These rules are NOT checked, but they must be carefully
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* applied by software that uses MXS DMA channels.
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*
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* Invariant:
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* The DMA channel's hardware semaphore must reflect the number of DMA
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* commands the hardware will process, but has not yet finished.
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*
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* Explanation:
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* A DMA channel begins processing commands when its hardware semaphore is
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* written with a value greater than zero, and it stops processing commands
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* when the semaphore returns to zero.
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*
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* When a channel finishes a DMA command, it will decrement its semaphore if
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* the DECREMENT_SEMAPHORE bit is set in that command's flags bits.
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*
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* In principle, it's not necessary for the DECREMENT_SEMAPHORE to be set,
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* unless it suits the purposes of the software. For example, one could
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* construct a series of five DMA commands, with the DECREMENT_SEMAPHORE
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* bit set only in the last one. Then, setting the DMA channel's hardware
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* semaphore to one would cause the entire series of five commands to be
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* processed. However, this example would violate the invariant given above.
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*
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* Rule:
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* ALL DMA commands MUST have the DECREMENT_SEMAPHORE bit set so that the DMA
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* channel's hardware semaphore will be decremented EVERY time a command is
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* processed.
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*/
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int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc)
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{
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struct mxs_dma_chan *pchan;
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struct mxs_dma_desc *last;
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int ret;
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ret = mxs_dma_validate_chan(channel);
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if (ret)
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return ret;
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pchan = mxs_dma_channels + channel;
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pdesc->cmd.next = mxs_dma_cmd_address(pdesc);
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pdesc->flags |= MXS_DMA_DESC_FIRST | MXS_DMA_DESC_LAST;
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if (!list_empty(&pchan->active)) {
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last = list_entry(pchan->active.prev, struct mxs_dma_desc,
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node);
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pdesc->flags &= ~MXS_DMA_DESC_FIRST;
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last->flags &= ~MXS_DMA_DESC_LAST;
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last->cmd.next = mxs_dma_cmd_address(pdesc);
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last->cmd.data |= MXS_DMA_DESC_CHAIN;
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mxs_dma_flush_desc(last);
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}
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pdesc->flags |= MXS_DMA_DESC_READY;
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if (pdesc->flags & MXS_DMA_DESC_FIRST)
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pchan->pending_num++;
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list_add_tail(&pdesc->node, &pchan->active);
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mxs_dma_flush_desc(pdesc);
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return ret;
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}
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/*
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* Clean up processed DMA descriptors.
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*
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* This function removes processed DMA descriptors from the "active" list. Pass
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* in a non-NULL list head to get the descriptors moved to your list. Pass NULL
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* to get the descriptors moved to the channel's "done" list. Descriptors on
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* the "done" list can be retrieved with mxs_dma_get_finished().
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*
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* This function marks the DMA channel as "not busy" if no unprocessed
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* descriptors remain on the "active" list.
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*/
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static int mxs_dma_finish(int channel, struct list_head *head)
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{
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int sem;
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struct mxs_dma_chan *pchan;
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struct list_head *p, *q;
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struct mxs_dma_desc *pdesc;
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int ret;
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ret = mxs_dma_validate_chan(channel);
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if (ret)
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return ret;
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pchan = mxs_dma_channels + channel;
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sem = mxs_dma_read_semaphore(channel);
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if (sem < 0)
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return sem;
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if (sem == pchan->active_num)
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return 0;
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list_for_each_safe(p, q, &pchan->active) {
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if ((pchan->active_num) <= sem)
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break;
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pdesc = list_entry(p, struct mxs_dma_desc, node);
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pdesc->flags &= ~MXS_DMA_DESC_READY;
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if (head)
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list_move_tail(p, head);
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else
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list_move_tail(p, &pchan->done);
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if (pdesc->flags & MXS_DMA_DESC_LAST)
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pchan->active_num--;
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}
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if (sem == 0)
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pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
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return 0;
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}
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/*
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* Wait for DMA channel to complete
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*/
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static int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan)
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{
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struct mxs_apbh_regs *apbh_regs =
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(struct mxs_apbh_regs *)MXS_APBH_BASE;
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int ret;
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ret = mxs_dma_validate_chan(chan);
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if (ret)
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return ret;
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if (mxs_wait_mask_set(&apbh_regs->hw_apbh_ctrl1_reg,
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1 << chan, timeout)) {
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ret = -ETIMEDOUT;
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mxs_dma_reset(chan);
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}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Execute the DMA channel
|
|
*/
|
|
int mxs_dma_go(int chan)
|
|
{
|
|
uint32_t timeout = 10000000;
|
|
int ret;
|
|
|
|
LIST_HEAD(tmp_desc_list);
|
|
|
|
mxs_dma_enable_irq(chan, 1);
|
|
mxs_dma_enable(chan);
|
|
|
|
/* Wait for DMA to finish. */
|
|
ret = mxs_dma_wait_complete(timeout, chan);
|
|
|
|
/* Clear out the descriptors we just ran. */
|
|
mxs_dma_finish(chan, &tmp_desc_list);
|
|
|
|
/* Shut the DMA channel down. */
|
|
mxs_dma_ack_irq(chan);
|
|
mxs_dma_reset(chan);
|
|
mxs_dma_enable_irq(chan, 0);
|
|
mxs_dma_disable(chan);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Execute a continuously running circular DMA descriptor.
|
|
* NOTE: This is not intended for general use, but rather
|
|
* for the LCD driver in Smart-LCD mode. It allows
|
|
* continuous triggering of the RUN bit there.
|
|
*/
|
|
void mxs_dma_circ_start(int chan, struct mxs_dma_desc *pdesc)
|
|
{
|
|
struct mxs_apbh_regs *apbh_regs =
|
|
(struct mxs_apbh_regs *)MXS_APBH_BASE;
|
|
|
|
mxs_dma_flush_desc(pdesc);
|
|
|
|
mxs_dma_enable_irq(chan, 1);
|
|
|
|
writel(mxs_dma_cmd_address(pdesc),
|
|
&apbh_regs->ch[chan].hw_apbh_ch_nxtcmdar);
|
|
writel(1, &apbh_regs->ch[chan].hw_apbh_ch_sema);
|
|
writel(1 << (chan + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),
|
|
&apbh_regs->hw_apbh_ctrl0_clr);
|
|
}
|
|
|
|
/*
|
|
* Initialize the DMA hardware
|
|
*/
|
|
void mxs_dma_init(void)
|
|
{
|
|
struct mxs_apbh_regs *apbh_regs =
|
|
(struct mxs_apbh_regs *)MXS_APBH_BASE;
|
|
|
|
mxs_reset_block(&apbh_regs->hw_apbh_ctrl0_reg);
|
|
|
|
#ifdef CONFIG_APBH_DMA_BURST8
|
|
writel(APBH_CTRL0_AHB_BURST8_EN,
|
|
&apbh_regs->hw_apbh_ctrl0_set);
|
|
#else
|
|
writel(APBH_CTRL0_AHB_BURST8_EN,
|
|
&apbh_regs->hw_apbh_ctrl0_clr);
|
|
#endif
|
|
|
|
#ifdef CONFIG_APBH_DMA_BURST
|
|
writel(APBH_CTRL0_APB_BURST_EN,
|
|
&apbh_regs->hw_apbh_ctrl0_set);
|
|
#else
|
|
writel(APBH_CTRL0_APB_BURST_EN,
|
|
&apbh_regs->hw_apbh_ctrl0_clr);
|
|
#endif
|
|
}
|
|
|
|
int mxs_dma_init_channel(int channel)
|
|
{
|
|
struct mxs_dma_chan *pchan;
|
|
int ret;
|
|
|
|
pchan = mxs_dma_channels + channel;
|
|
pchan->flags = MXS_DMA_FLAGS_VALID;
|
|
|
|
ret = mxs_dma_request(channel);
|
|
|
|
if (ret) {
|
|
printf("MXS DMA: Can't acquire DMA channel %i\n",
|
|
channel);
|
|
return ret;
|
|
}
|
|
|
|
mxs_dma_reset(channel);
|
|
mxs_dma_ack_irq(channel);
|
|
|
|
return 0;
|
|
}
|