mirror of
https://github.com/AsahiLinux/u-boot
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e809e74799
The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
596 lines
15 KiB
C
596 lines
15 KiB
C
/*
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* Copyright 2017 NXP
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* Copyright 2014-2015 Freescale Semiconductor, Inc.
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* Layerscape PCIe driver
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/fsl_serdes.h>
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#include <pci.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <malloc.h>
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#include <dm.h>
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#include "pcie_layerscape.h"
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DECLARE_GLOBAL_DATA_PTR;
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LIST_HEAD(ls_pcie_list);
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static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset)
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{
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return in_le32(pcie->dbi + offset);
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}
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static void dbi_writel(struct ls_pcie *pcie, unsigned int value,
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unsigned int offset)
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{
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out_le32(pcie->dbi + offset, value);
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}
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static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset)
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{
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if (pcie->big_endian)
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return in_be32(pcie->ctrl + offset);
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else
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return in_le32(pcie->ctrl + offset);
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}
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static void ctrl_writel(struct ls_pcie *pcie, unsigned int value,
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unsigned int offset)
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{
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if (pcie->big_endian)
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out_be32(pcie->ctrl + offset, value);
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else
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out_le32(pcie->ctrl + offset, value);
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}
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static int ls_pcie_ltssm(struct ls_pcie *pcie)
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{
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u32 state;
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uint svr;
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svr = get_svr();
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if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) {
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state = ctrl_readl(pcie, LS1021_PEXMSCPORTSR(pcie->idx));
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state = (state >> LS1021_LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
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} else {
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state = ctrl_readl(pcie, PCIE_PF_DBG) & LTSSM_STATE_MASK;
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}
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return state;
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}
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static int ls_pcie_link_up(struct ls_pcie *pcie)
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{
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int ltssm;
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ltssm = ls_pcie_ltssm(pcie);
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if (ltssm < LTSSM_PCIE_L0)
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return 0;
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return 1;
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}
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static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
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{
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dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
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PCIE_ATU_VIEWPORT);
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dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
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}
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static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev)
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{
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dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
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PCIE_ATU_VIEWPORT);
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dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
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}
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static void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
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u64 phys, u64 bus_addr, pci_size_t size)
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{
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dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | idx, PCIE_ATU_VIEWPORT);
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dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_BASE);
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dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_BASE);
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dbi_writel(pcie, (u32)phys + size - 1, PCIE_ATU_LIMIT);
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dbi_writel(pcie, (u32)bus_addr, PCIE_ATU_LOWER_TARGET);
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dbi_writel(pcie, bus_addr >> 32, PCIE_ATU_UPPER_TARGET);
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dbi_writel(pcie, type, PCIE_ATU_CR1);
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dbi_writel(pcie, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
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}
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/* Use bar match mode and MEM type as default */
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static void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx,
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int bar, u64 phys)
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{
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dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT);
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dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET);
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dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET);
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dbi_writel(pcie, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
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dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
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PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2);
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}
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static void ls_pcie_dump_atu(struct ls_pcie *pcie)
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{
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int i;
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for (i = 0; i < PCIE_ATU_REGION_NUM; i++) {
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dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | i,
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PCIE_ATU_VIEWPORT);
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debug("iATU%d:\n", i);
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debug("\tLOWER PHYS 0x%08x\n",
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dbi_readl(pcie, PCIE_ATU_LOWER_BASE));
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debug("\tUPPER PHYS 0x%08x\n",
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dbi_readl(pcie, PCIE_ATU_UPPER_BASE));
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debug("\tLOWER BUS 0x%08x\n",
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dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
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debug("\tUPPER BUS 0x%08x\n",
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dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
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debug("\tLIMIT 0x%08x\n",
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readl(pcie->dbi + PCIE_ATU_LIMIT));
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debug("\tCR1 0x%08x\n",
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dbi_readl(pcie, PCIE_ATU_CR1));
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debug("\tCR2 0x%08x\n",
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dbi_readl(pcie, PCIE_ATU_CR2));
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}
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}
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static void ls_pcie_setup_atu(struct ls_pcie *pcie)
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{
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struct pci_region *io, *mem, *pref;
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unsigned long long offset = 0;
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int idx = 0;
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uint svr;
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svr = get_svr();
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if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) {
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offset = LS1021_PCIE_SPACE_OFFSET +
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LS1021_PCIE_SPACE_SIZE * pcie->idx;
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}
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/* ATU 0 : OUTBOUND : CFG0 */
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ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
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PCIE_ATU_TYPE_CFG0,
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pcie->cfg_res.start + offset,
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0,
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fdt_resource_size(&pcie->cfg_res) / 2);
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/* ATU 1 : OUTBOUND : CFG1 */
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ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
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PCIE_ATU_TYPE_CFG1,
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pcie->cfg_res.start + offset +
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fdt_resource_size(&pcie->cfg_res) / 2,
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0,
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fdt_resource_size(&pcie->cfg_res) / 2);
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pci_get_regions(pcie->bus, &io, &mem, &pref);
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idx = PCIE_ATU_REGION_INDEX1 + 1;
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/* Fix the pcie memory map for LS2088A series SoCs */
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svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
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if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
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svr == SVR_LS2048A || svr == SVR_LS2044A ||
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svr == SVR_LS2081A || svr == SVR_LS2041A) {
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if (io)
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io->phys_start = (io->phys_start &
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(PCIE_PHYS_SIZE - 1)) +
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LS2088A_PCIE1_PHYS_ADDR +
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LS2088A_PCIE_PHYS_SIZE * pcie->idx;
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if (mem)
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mem->phys_start = (mem->phys_start &
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(PCIE_PHYS_SIZE - 1)) +
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LS2088A_PCIE1_PHYS_ADDR +
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LS2088A_PCIE_PHYS_SIZE * pcie->idx;
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if (pref)
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pref->phys_start = (pref->phys_start &
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(PCIE_PHYS_SIZE - 1)) +
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LS2088A_PCIE1_PHYS_ADDR +
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LS2088A_PCIE_PHYS_SIZE * pcie->idx;
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}
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if (io)
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/* ATU : OUTBOUND : IO */
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ls_pcie_atu_outbound_set(pcie, idx++,
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PCIE_ATU_TYPE_IO,
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io->phys_start + offset,
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io->bus_start,
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io->size);
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if (mem)
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/* ATU : OUTBOUND : MEM */
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ls_pcie_atu_outbound_set(pcie, idx++,
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PCIE_ATU_TYPE_MEM,
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mem->phys_start + offset,
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mem->bus_start,
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mem->size);
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if (pref)
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/* ATU : OUTBOUND : pref */
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ls_pcie_atu_outbound_set(pcie, idx++,
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PCIE_ATU_TYPE_MEM,
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pref->phys_start + offset,
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pref->bus_start,
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pref->size);
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ls_pcie_dump_atu(pcie);
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}
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/* Return 0 if the address is valid, -errno if not valid */
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static int ls_pcie_addr_valid(struct ls_pcie *pcie, pci_dev_t bdf)
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{
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struct udevice *bus = pcie->bus;
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if (!pcie->enabled)
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return -ENXIO;
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if (PCI_BUS(bdf) < bus->seq)
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return -EINVAL;
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if ((PCI_BUS(bdf) > bus->seq) && (!ls_pcie_link_up(pcie)))
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return -EINVAL;
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if (PCI_BUS(bdf) <= (bus->seq + 1) && (PCI_DEV(bdf) > 0))
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return -EINVAL;
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return 0;
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}
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void *ls_pcie_conf_address(struct ls_pcie *pcie, pci_dev_t bdf,
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int offset)
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{
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struct udevice *bus = pcie->bus;
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u32 busdev;
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if (PCI_BUS(bdf) == bus->seq)
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return pcie->dbi + offset;
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busdev = PCIE_ATU_BUS(PCI_BUS(bdf)) |
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PCIE_ATU_DEV(PCI_DEV(bdf)) |
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PCIE_ATU_FUNC(PCI_FUNC(bdf));
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if (PCI_BUS(bdf) == bus->seq + 1) {
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ls_pcie_cfg0_set_busdev(pcie, busdev);
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return pcie->cfg0 + offset;
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} else {
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ls_pcie_cfg1_set_busdev(pcie, busdev);
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return pcie->cfg1 + offset;
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}
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}
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static int ls_pcie_read_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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struct ls_pcie *pcie = dev_get_priv(bus);
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void *address;
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if (ls_pcie_addr_valid(pcie, bdf)) {
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*valuep = pci_get_ff(size);
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return 0;
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}
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address = ls_pcie_conf_address(pcie, bdf, offset);
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switch (size) {
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case PCI_SIZE_8:
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*valuep = readb(address);
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return 0;
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case PCI_SIZE_16:
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*valuep = readw(address);
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return 0;
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case PCI_SIZE_32:
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*valuep = readl(address);
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return 0;
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default:
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return -EINVAL;
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}
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}
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static int ls_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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struct ls_pcie *pcie = dev_get_priv(bus);
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void *address;
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if (ls_pcie_addr_valid(pcie, bdf))
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return 0;
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address = ls_pcie_conf_address(pcie, bdf, offset);
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switch (size) {
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case PCI_SIZE_8:
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writeb(value, address);
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return 0;
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case PCI_SIZE_16:
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writew(value, address);
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return 0;
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case PCI_SIZE_32:
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writel(value, address);
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return 0;
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default:
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return -EINVAL;
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}
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}
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/* Clear multi-function bit */
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static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
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{
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writeb(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE);
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}
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/* Fix class value */
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static void ls_pcie_fix_class(struct ls_pcie *pcie)
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{
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writew(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE);
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}
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/* Drop MSG TLP except for Vendor MSG */
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static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
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{
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u32 val;
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val = dbi_readl(pcie, PCIE_STRFMR1);
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val &= 0xDFFFFFFF;
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dbi_writel(pcie, val, PCIE_STRFMR1);
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}
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/* Disable all bars in RC mode */
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static void ls_pcie_disable_bars(struct ls_pcie *pcie)
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{
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u32 sriov;
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sriov = in_le32(pcie->dbi + PCIE_SRIOV);
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/*
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* TODO: For PCIe controller with SRIOV, the method to disable bars
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* is different and more complex, so will add later.
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*/
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if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV)
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return;
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dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_0);
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dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_1);
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dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1);
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}
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static void ls_pcie_setup_ctrl(struct ls_pcie *pcie)
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{
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ls_pcie_setup_atu(pcie);
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dbi_writel(pcie, 1, PCIE_DBI_RO_WR_EN);
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ls_pcie_fix_class(pcie);
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ls_pcie_clear_multifunction(pcie);
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ls_pcie_drop_msg_tlp(pcie);
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dbi_writel(pcie, 0, PCIE_DBI_RO_WR_EN);
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ls_pcie_disable_bars(pcie);
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}
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static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie)
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{
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u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE;
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/* ATU 0 : INBOUND : map BAR0 */
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ls_pcie_atu_inbound_set(pcie, 0, 0, phys);
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/* ATU 1 : INBOUND : map BAR1 */
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phys += PCIE_BAR1_SIZE;
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ls_pcie_atu_inbound_set(pcie, 1, 1, phys);
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/* ATU 2 : INBOUND : map BAR2 */
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phys += PCIE_BAR2_SIZE;
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ls_pcie_atu_inbound_set(pcie, 2, 2, phys);
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/* ATU 3 : INBOUND : map BAR4 */
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phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE;
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ls_pcie_atu_inbound_set(pcie, 3, 4, phys);
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/* ATU 0 : OUTBOUND : map MEM */
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ls_pcie_atu_outbound_set(pcie, 0,
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PCIE_ATU_TYPE_MEM,
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pcie->cfg_res.start,
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0,
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CONFIG_SYS_PCI_MEMORY_SIZE);
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}
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/* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
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static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
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{
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/* The least inbound window is 4KiB */
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if (size < 4 * 1024)
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return;
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switch (bar) {
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case 0:
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writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
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break;
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case 1:
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writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
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break;
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case 2:
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writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
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writel(0, bar_base + PCI_BASE_ADDRESS_3);
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break;
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case 4:
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writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
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writel(0, bar_base + PCI_BASE_ADDRESS_5);
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break;
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default:
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break;
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}
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}
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static void ls_pcie_ep_setup_bars(void *bar_base)
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{
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/* BAR0 - 32bit - 4K configuration */
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ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
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/* BAR1 - 32bit - 8K MSIX*/
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ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
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/* BAR2 - 64bit - 4K MEM desciptor */
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ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
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/* BAR4 - 64bit - 1M MEM*/
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ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
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}
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static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie)
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{
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ctrl_writel(pcie, PCIE_CONFIG_READY, PCIE_PF_CONFIG);
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}
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static void ls_pcie_setup_ep(struct ls_pcie *pcie)
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{
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u32 sriov;
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sriov = readl(pcie->dbi + PCIE_SRIOV);
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if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) {
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int pf, vf;
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for (pf = 0; pf < PCIE_PF_NUM; pf++) {
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for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
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ctrl_writel(pcie, PCIE_LCTRL0_VAL(pf, vf),
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PCIE_PF_VF_CTRL);
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ls_pcie_ep_setup_bars(pcie->dbi);
|
|
ls_pcie_ep_setup_atu(pcie);
|
|
}
|
|
}
|
|
/* Disable CFG2 */
|
|
ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL);
|
|
} else {
|
|
ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
|
|
ls_pcie_ep_setup_atu(pcie);
|
|
}
|
|
|
|
ls_pcie_ep_enable_cfg(pcie);
|
|
}
|
|
|
|
static int ls_pcie_probe(struct udevice *dev)
|
|
{
|
|
struct ls_pcie *pcie = dev_get_priv(dev);
|
|
const void *fdt = gd->fdt_blob;
|
|
int node = dev_of_offset(dev);
|
|
u8 header_type;
|
|
u16 link_sta;
|
|
bool ep_mode;
|
|
uint svr;
|
|
int ret;
|
|
|
|
pcie->bus = dev;
|
|
|
|
ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
|
|
"dbi", &pcie->dbi_res);
|
|
if (ret) {
|
|
printf("ls-pcie: resource \"dbi\" not found\n");
|
|
return ret;
|
|
}
|
|
|
|
pcie->idx = (pcie->dbi_res.start - PCIE_SYS_BASE_ADDR) / PCIE_CCSR_SIZE;
|
|
|
|
list_add(&pcie->list, &ls_pcie_list);
|
|
|
|
pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
|
|
if (!pcie->enabled) {
|
|
printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
|
|
return 0;
|
|
}
|
|
|
|
pcie->dbi = map_physmem(pcie->dbi_res.start,
|
|
fdt_resource_size(&pcie->dbi_res),
|
|
MAP_NOCACHE);
|
|
|
|
ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
|
|
"lut", &pcie->lut_res);
|
|
if (!ret)
|
|
pcie->lut = map_physmem(pcie->lut_res.start,
|
|
fdt_resource_size(&pcie->lut_res),
|
|
MAP_NOCACHE);
|
|
|
|
ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
|
|
"ctrl", &pcie->ctrl_res);
|
|
if (!ret)
|
|
pcie->ctrl = map_physmem(pcie->ctrl_res.start,
|
|
fdt_resource_size(&pcie->ctrl_res),
|
|
MAP_NOCACHE);
|
|
if (!pcie->ctrl)
|
|
pcie->ctrl = pcie->lut;
|
|
|
|
if (!pcie->ctrl) {
|
|
printf("%s: NOT find CTRL\n", dev->name);
|
|
return -1;
|
|
}
|
|
|
|
ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
|
|
"config", &pcie->cfg_res);
|
|
if (ret) {
|
|
printf("%s: resource \"config\" not found\n", dev->name);
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Fix the pcie memory map address and PF control registers address
|
|
* for LS2088A series SoCs
|
|
*/
|
|
svr = get_svr();
|
|
svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
|
|
if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
|
|
svr == SVR_LS2048A || svr == SVR_LS2044A ||
|
|
svr == SVR_LS2081A || svr == SVR_LS2041A) {
|
|
pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
|
|
LS2088A_PCIE_PHYS_SIZE * pcie->idx;
|
|
pcie->ctrl = pcie->lut + 0x40000;
|
|
}
|
|
|
|
pcie->cfg0 = map_physmem(pcie->cfg_res.start,
|
|
fdt_resource_size(&pcie->cfg_res),
|
|
MAP_NOCACHE);
|
|
pcie->cfg1 = pcie->cfg0 + fdt_resource_size(&pcie->cfg_res) / 2;
|
|
|
|
pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
|
|
|
|
debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n",
|
|
dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut,
|
|
(unsigned long)pcie->ctrl, (unsigned long)pcie->cfg0,
|
|
pcie->big_endian);
|
|
|
|
header_type = readb(pcie->dbi + PCI_HEADER_TYPE);
|
|
ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
|
|
printf("PCIe%u: %s %s", pcie->idx, dev->name,
|
|
ep_mode ? "Endpoint" : "Root Complex");
|
|
|
|
if (ep_mode)
|
|
ls_pcie_setup_ep(pcie);
|
|
else
|
|
ls_pcie_setup_ctrl(pcie);
|
|
|
|
if (!ls_pcie_link_up(pcie)) {
|
|
/* Let the user know there's no PCIe link */
|
|
printf(": no link\n");
|
|
return 0;
|
|
}
|
|
|
|
/* Print the negotiated PCIe link width */
|
|
link_sta = readw(pcie->dbi + PCIE_LINK_STA);
|
|
printf(": x%d gen%d\n", (link_sta & PCIE_LINK_WIDTH_MASK) >> 4,
|
|
link_sta & PCIE_LINK_SPEED_MASK);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dm_pci_ops ls_pcie_ops = {
|
|
.read_config = ls_pcie_read_config,
|
|
.write_config = ls_pcie_write_config,
|
|
};
|
|
|
|
static const struct udevice_id ls_pcie_ids[] = {
|
|
{ .compatible = "fsl,ls-pcie" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(pci_layerscape) = {
|
|
.name = "pci_layerscape",
|
|
.id = UCLASS_PCI,
|
|
.of_match = ls_pcie_ids,
|
|
.ops = &ls_pcie_ops,
|
|
.probe = ls_pcie_probe,
|
|
.priv_auto_alloc_size = sizeof(struct ls_pcie),
|
|
};
|