mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-21 15:12:04 +00:00
2509493cc1
TFTP transfer size can be used to re-size the TFTP progress bar on single line based on the server reported file size. The support for this has been around from 2019, but it was never converted to proper Kconfig. While adding this new Kconfig, enable it by default for OMAP2+ and K3 devices also. Signed-off-by: Tero Kristo <kristo@kernel.org>
142 lines
4.3 KiB
C
142 lines
4.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2019 Toradex
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*/
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#ifndef __COLIBRI_IMX8X_H
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#define __COLIBRI_IMX8X_H
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#include <asm/arch/imx-regs.h>
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#include <linux/sizes.h>
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#include <linux/stringify.h>
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#define CONFIG_REMAKE_ELF
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#define CONFIG_DISPLAY_BOARDINFO_LATE
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define USDHC1_BASE_ADDR 0x5b010000
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#define USDHC2_BASE_ADDR 0x5b020000
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#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
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#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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#define CONFIG_IPADDR 192.168.10.2
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_SERVERIP 192.168.10.1
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#define MEM_LAYOUT_ENV_SETTINGS \
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"fdt_addr_r=0x83000000\0" \
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"kernel_addr_r=0x81000000\0" \
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"ramdisk_addr_r=0x83800000\0" \
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"scriptaddr=0x80800000\0"
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#ifdef CONFIG_AHAB_BOOT
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#define AHAB_ENV "sec_boot=yes\0"
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#else
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#define AHAB_ENV "sec_boot=no\0"
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#endif
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/* Boot M4 */
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#define M4_BOOT_ENV \
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"m4_0_image=m4_0.bin\0" \
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"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
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"${m4_0_image}\0" \
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"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
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#define MFG_NAND_PARTITION ""
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 1) \
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func(MMC, mmc, 0) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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#undef BOOTENV_RUN_NET_USB_START
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#define BOOTENV_RUN_NET_USB_START ""
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#define CONFIG_MFG_ENV_SETTINGS \
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"mfgtool_args=setenv bootargs ${consoleargs} " \
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"rdinit=/linuxrc g_mass_storage.stall=0 " \
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"g_mass_storage.removable=1 g_mass_storage.idVendor=0x066F " \
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"g_mass_storage.idProduct=0x37FF " \
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"g_mass_storage.iSerialNumber=\"\" " MFG_NAND_PARTITION \
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"${vidargs} clk_ignore_unused\0" \
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"initrd_addr=0x83800000\0" \
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"initrd_high=0xffffffff\0" \
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"bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} " \
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"${fdt_addr};\0" \
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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AHAB_ENV \
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BOOTENV \
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CONFIG_MFG_ENV_SETTINGS \
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M4_BOOT_ENV \
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MEM_LAYOUT_ENV_SETTINGS \
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"boot_file=Image\0" \
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"consoleargs=console=ttyLP3,${baudrate} earlycon\0" \
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"fdt_addr=0x83000000\0" \
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"fdt_file=fsl-imx8qxp-colibri-dsihdmi-eval-v3.dtb\0" \
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"fdtfile=fsl-imx8qxp-colibri-dsihdmi-eval-v3.dtb\0" \
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"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
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"image=Image\0" \
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"initrd_addr=0x83800000\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"mmcargs=setenv bootargs ${consoleargs} " \
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"root=PARTUUID=${uuid} rootwait " \
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"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
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"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
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"netargs=setenv bootargs ${consoleargs} " \
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"root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \
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"${vidargs}\0" \
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"nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \
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"colibri-imx8x/${fdt_file}; booti ${loadaddr} - " \
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"${fdt_addr}\0" \
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"panel=NULL\0" \
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"script=boot.scr\0" \
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"update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \
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"if test \"$confirm\" = \"y\"; then " \
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"setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
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"${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \
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"${blkcnt}; fi\0" \
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"vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0"
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/* Link Definitions */
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#define CONFIG_LOADADDR 0x80280000
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
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/* Environment in eMMC, before config block at the end of 1st "boot sector" */
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#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
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/* On Colibri iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define PHYS_SDRAM_1 0x80000000
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#define PHYS_SDRAM_2 0x880000000
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#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */
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#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE SZ_2K
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#define CONFIG_SYS_MAXARGS 64
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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/* Generic Timer Definitions */
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#define COUNTER_FREQUENCY 8000000 /* 8MHz */
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#define BOOTAUX_RESERVED_MEM_BASE 0x88000000
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#define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */
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#endif /* __COLIBRI_IMX8X_H */
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