mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-14 15:23:07 +00:00
e8cd1f60d9
1. Implement bootaux for the M4 boot on i.MX8QM and QXP. Users need to download M4 image to any DDR address first. Then use the "bootaux <M4 download DDR address> [M4 core id]" to boot CM4_0 or CM4_1, the default core id is 0 for CM4_0. Since current M4 only supports running in TCM. The bootaux will copy the M4 image from DDR to its TCML. 2. Implment bootaux for HIFI on QXP command: bootaux 0x81000000 1 Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
278 lines
8.6 KiB
C
278 lines
8.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2009
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*/
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#ifndef _SYS_PROTO_H_
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#define _SYS_PROTO_H_
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#include <asm/io.h>
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#include <asm/mach-imx/regs-common.h>
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#include <asm/mach-imx/module_fuse.h>
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#include <linux/bitops.h>
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#include "../arch-imx/cpu.h"
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struct bd_info;
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#define soc_rev() (get_cpu_rev() & 0xFF)
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#define is_soc_rev(rev) (soc_rev() == rev)
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/* returns MXC_CPU_ value */
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#define cpu_type(rev) (((rev) >> 12) & 0x1ff)
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#define soc_type(rev) (((rev) >> 12) & 0xf0)
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/* both macros return/take MXC_CPU_ constants */
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#define get_cpu_type() (cpu_type(get_cpu_rev()))
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#define get_soc_type() (soc_type(get_cpu_rev()))
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#define is_cpu_type(cpu) (get_cpu_type() == cpu)
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#define is_soc_type(soc) (get_soc_type() == soc)
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#define is_mx6() (is_soc_type(MXC_SOC_MX6))
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#define is_mx7() (is_soc_type(MXC_SOC_MX7))
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#define is_imx8m() (is_soc_type(MXC_SOC_IMX8M))
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#define is_imx8() (is_soc_type(MXC_SOC_IMX8))
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#define is_imx9() (is_soc_type(MXC_SOC_IMX9))
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#define is_imxrt() (is_soc_type(MXC_SOC_IMXRT))
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#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
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#define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
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#define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL))
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#define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL))
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#define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX))
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#define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
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#define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO))
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#define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
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#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL) || is_cpu_type(MXC_CPU_MX6ULZ))
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#define is_mx6ulz() (is_cpu_type(MXC_CPU_MX6ULZ))
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#define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL))
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#define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
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#define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ) || is_cpu_type(MXC_CPU_IMX8MD) || is_cpu_type(MXC_CPU_IMX8MQL))
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#define is_imx8md() (is_cpu_type(MXC_CPU_IMX8MD))
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#define is_imx8mql() (is_cpu_type(MXC_CPU_IMX8MQL))
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#define is_imx8qm() (is_cpu_type(MXC_CPU_IMX8QM))
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#define is_imx8ulp() (is_cpu_type(MXC_CPU_IMX8ULP))
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#define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) || is_cpu_type(MXC_CPU_IMX8MML) ||\
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is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \
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is_cpu_type(MXC_CPU_IMX8MMS) || is_cpu_type(MXC_CPU_IMX8MMSL))
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#define is_imx8mml() (is_cpu_type(MXC_CPU_IMX8MML))
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#define is_imx8mmd() (is_cpu_type(MXC_CPU_IMX8MMD))
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#define is_imx8mmdl() (is_cpu_type(MXC_CPU_IMX8MMDL))
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#define is_imx8mms() (is_cpu_type(MXC_CPU_IMX8MMS))
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#define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL))
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#define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN) || is_cpu_type(MXC_CPU_IMX8MND) || \
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is_cpu_type(MXC_CPU_IMX8MNS) || is_cpu_type(MXC_CPU_IMX8MNL) || \
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is_cpu_type(MXC_CPU_IMX8MNDL) || is_cpu_type(MXC_CPU_IMX8MNSL) || \
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is_cpu_type(MXC_CPU_IMX8MNUD) || is_cpu_type(MXC_CPU_IMX8MNUS) || is_cpu_type(MXC_CPU_IMX8MNUQ))
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#define is_imx8mnd() (is_cpu_type(MXC_CPU_IMX8MND))
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#define is_imx8mns() (is_cpu_type(MXC_CPU_IMX8MNS))
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#define is_imx8mnl() (is_cpu_type(MXC_CPU_IMX8MNL))
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#define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL))
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#define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL))
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#define is_imx8mnuq() (is_cpu_type(MXC_CPU_IMX8MNUQ))
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#define is_imx8mnud() (is_cpu_type(MXC_CPU_IMX8MNUD))
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#define is_imx8mnus() (is_cpu_type(MXC_CPU_IMX8MNUS))
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#define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP) || is_cpu_type(MXC_CPU_IMX8MPD) || \
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is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6) || is_cpu_type(MXC_CPU_IMX8MPUL))
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#define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD))
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#define is_imx8mpl() (is_cpu_type(MXC_CPU_IMX8MPL))
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#define is_imx8mp6() (is_cpu_type(MXC_CPU_IMX8MP6))
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#define is_imx8mpul() (is_cpu_type(MXC_CPU_IMX8MPUL))
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#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
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#define is_imx93() (is_cpu_type(MXC_CPU_IMX93) || is_cpu_type(MXC_CPU_IMX9331) || \
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is_cpu_type(MXC_CPU_IMX9332) || is_cpu_type(MXC_CPU_IMX9351) || \
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is_cpu_type(MXC_CPU_IMX9322) || is_cpu_type(MXC_CPU_IMX9321) || \
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is_cpu_type(MXC_CPU_IMX9312) || is_cpu_type(MXC_CPU_IMX9311))
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#define is_imx9351() (is_cpu_type(MXC_CPU_IMX9351))
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#define is_imx9332() (is_cpu_type(MXC_CPU_IMX9332))
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#define is_imx9331() (is_cpu_type(MXC_CPU_IMX9331))
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#define is_imx9322() (is_cpu_type(MXC_CPU_IMX9322))
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#define is_imx9321() (is_cpu_type(MXC_CPU_IMX9321))
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#define is_imx9312() (is_cpu_type(MXC_CPU_IMX9312))
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#define is_imx9311() (is_cpu_type(MXC_CPU_IMX9311))
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#define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020))
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#define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050))
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#ifdef CONFIG_MX6
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#define IMX6_SRC_GPR10_BMODE BIT(28)
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#define IMX6_SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30)
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#define IMX6_BMODE_MASK GENMASK(7, 0)
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#define IMX6_BMODE_SHIFT 4
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#define IMX6_BMODE_EIM_MASK BIT(3)
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#define IMX6_BMODE_EIM_SHIFT 3
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#define IMX6_BMODE_SERIAL_ROM_MASK GENMASK(26, 24)
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#define IMX6_BMODE_SERIAL_ROM_SHIFT 24
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enum imx6_bmode_serial_rom {
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IMX6_BMODE_ECSPI1,
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IMX6_BMODE_ECSPI2,
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IMX6_BMODE_ECSPI3,
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IMX6_BMODE_ECSPI4,
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IMX6_BMODE_ECSPI5,
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IMX6_BMODE_I2C1,
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IMX6_BMODE_I2C2,
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IMX6_BMODE_I2C3,
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};
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enum imx6_bmode_eim {
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IMX6_BMODE_NOR,
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IMX6_BMODE_ONENAND,
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};
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enum imx6_bmode {
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IMX6_BMODE_EIM,
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#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
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IMX6_BMODE_QSPI,
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IMX6_BMODE_RESERVED,
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#else
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IMX6_BMODE_RESERVED,
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IMX6_BMODE_SATA,
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#endif
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IMX6_BMODE_SERIAL_ROM,
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IMX6_BMODE_SD,
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IMX6_BMODE_ESD,
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IMX6_BMODE_MMC,
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IMX6_BMODE_EMMC,
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IMX6_BMODE_NAND_MIN,
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IMX6_BMODE_NAND_MAX = 0xf,
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};
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u32 imx6_src_get_boot_mode(void);
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void gpr_init(void);
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#endif /* CONFIG_MX6 */
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#ifdef CONFIG_MX7
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#define IMX7_SRC_GPR10_BMODE BIT(28)
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#define IMX7_SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30)
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#endif
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/* address translation table */
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struct rproc_att {
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u32 da; /* device address (From Cortex M4 view) */
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u32 sa; /* system bus address */
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u32 size; /* size of reg range */
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};
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const struct rproc_att *imx_bootaux_get_hostmap(void);
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struct rom_api {
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u16 ver;
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u16 tag;
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u32 reserved1;
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u32 (*download_image)(u8 *dest, u32 offset, u32 size, u32 xor);
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u32 (*query_boot_infor)(u32 info_type, u32 *info, u32 xor);
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};
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enum boot_dev_type_e {
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BT_DEV_TYPE_SD = 1,
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BT_DEV_TYPE_MMC = 2,
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BT_DEV_TYPE_NAND = 3,
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BT_DEV_TYPE_FLEXSPINOR = 4,
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BT_DEV_TYPE_SPI_NOR = 6,
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BT_DEV_TYPE_USB = 0xE,
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BT_DEV_TYPE_MEM_DEV = 0xF,
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BT_DEV_TYPE_INVALID = 0xFF
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};
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enum boot_stage_type {
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BT_STAGE_PRIMARY = 0x6,
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BT_STAGE_SECONDARY = 0x9,
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BT_STAGE_RECOVERY = 0xa,
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BT_STAGE_USB = 0x5,
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};
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#define QUERY_ROM_VER 1
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#define QUERY_BT_DEV 2
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#define QUERY_PAGE_SZ 3
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#define QUERY_IVT_OFF 4
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#define QUERY_BT_STAGE 5
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#define QUERY_IMG_OFF 6
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#define ROM_API_OKAY 0xF0
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extern struct rom_api *g_rom_api;
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extern unsigned long rom_pointer[];
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ulong spl_romapi_raw_seekable_read(u32 offset, u32 size, void *buf);
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ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev);
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u32 rom_api_download_image(u8 *dest, u32 offset, u32 size);
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u32 rom_api_query_boot_infor(u32 info_type, u32 *info);
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/* For i.MX ULP */
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#define BT0CFG_LPBOOT_MASK 0x1
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#define BT0CFG_DUALBOOT_MASK 0x2
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enum bt_mode {
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LOW_POWER_BOOT, /* LP_BT = 1 */
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DUAL_BOOT, /* LP_BT = 0, DUAL_BT = 1 */
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SINGLE_BOOT /* LP_BT = 0, DUAL_BT = 0 */
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};
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u32 get_nr_cpus(void);
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u32 get_cpu_rev(void);
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u32 get_cpu_speed_grade_hz(void);
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u32 get_cpu_temp_grade(int *minc, int *maxc);
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const char *get_imx_type(u32 imxtype);
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u32 imx_ddr_size(void);
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void sdelay(unsigned long);
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void set_chipselect_size(int const);
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void init_aips(void);
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void init_src(void);
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void init_snvs(void);
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void imx_wdog_disable_powerdown(void);
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void board_mem_get_layout(u64 *phys_sdram_1_start,
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u64 *phys_sdram_1_size,
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u64 *phys_sdram_2_start,
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u64 *phys_sdram_2_size);
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int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data);
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int arch_auxiliary_core_check_up(u32 core_id);
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int board_mmc_get_env_dev(int devno);
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int nxp_board_rev(void);
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char nxp_board_rev_string(void);
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/*
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* Initializes on-chip ethernet controllers.
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* to override, implement board_eth_init()
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*/
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int fecmxc_initialize(struct bd_info *bis);
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u32 get_ahb_clk(void);
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u32 get_periph_clk(void);
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void lcdif_power_down(void);
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int mxs_reset_block(struct mxs_register_32 *reg);
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int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
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int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
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void board_late_mmc_env_init(void);
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unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
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unsigned long reg1, unsigned long reg2,
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unsigned long reg3);
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unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0,
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unsigned long *reg1, unsigned long reg2,
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unsigned long reg3);
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void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
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#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
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void enable_ca7_smp(void);
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#endif
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enum boot_device get_boot_device(void);
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#endif
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