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https://github.com/AsahiLinux/u-boot
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cf35290258
This patch is used to support DBD owner fuse changed to S400 only. The XRDC PDAC2 for LPAV pbridge5 and MSC1/2/3 for GPIO and LPAV are not configured by S400 default setting. So these PDAC and MSC are invalid, only DBD owner can access the corresponding resources. We have to configure necessary PDAC and MSC for SPL before DDR initialization. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
28 lines
894 B
C
28 lines
894 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2021 NXP
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*/
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#ifndef __ASM_ARCH_IMX8ULP_RDC_H
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#define __ASM_ARCH_IMX8ULP_RDC_H
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enum rdc_type {
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RDC_TRDC,
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RDC_XRDC,
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};
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int release_rdc(enum rdc_type type);
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void xrdc_mrc_region_set_access(int mrc_index, u32 addr, u32 access);
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int xrdc_config_mrc_dx_perm(u32 mrc_con, u32 region, u32 dom, u32 dxsel);
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int xrdc_config_mrc_w0_w1(u32 mrc_con, u32 region, u32 w0, u32 size);
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int xrdc_config_mrc_w3_w4(u32 mrc_con, u32 region, u32 w3, u32 w4);
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int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm);
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int xrdc_config_pdac_openacc(u32 bridge, u32 index);
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int trdc_mbc_set_access(u32 mbc_x, u32 dom_x, u32 mem_x, u32 blk_x, bool sec_access);
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int trdc_mrc_region_set_access(u32 mrc_x, u32 dom_x, u32 addr_start, u32 addr_end, bool sec_access);
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void xrdc_init_mda(void);
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void xrdc_init_mrc(void);
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void xrdc_init_pdac_msc(void);
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#endif
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