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418 lines
12 KiB
C
418 lines
12 KiB
C
/*
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* (C) Copyright 2001
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* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*************************************************************************
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* adaption for the Marvell DB64460 Board
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* Ingo Assmus (ingo.assmus@keymile.com)
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*************************************************************************/
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/* sdram_init.c - automatic memory sizing */
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#include <common.h>
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#include <74xx_7xx.h>
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#include "../../Marvell/include/memory.h"
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#include "../../Marvell/include/pci.h"
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#include "../../Marvell/include/mv_gen_reg.h"
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#include <net.h>
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#include "eth.h"
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#include "mpsc.h"
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#include "../../Marvell/common/i2c.h"
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#include "64460.h"
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#include "mv_regs.h"
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DECLARE_GLOBAL_DATA_PTR;
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#undef DEBUG
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#define MAP_PCI
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#ifdef DEBUG
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#define DP(x) x
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#else
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#define DP(x)
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#endif
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int set_dfcdlInit (void); /* setup delay line of Mv64460 */
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int mvDmaIsChannelActive (int);
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int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong);
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int mvDmaTransfer (int, ulong, ulong, ulong, ulong);
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#define D_CACHE_FLUSH_LINE(addr, offset) \
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{ \
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__asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
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}
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int memory_map_bank (unsigned int bankNo,
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unsigned int bankBase, unsigned int bankLength)
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{
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#if defined (MAP_PCI) && defined (CONFIG_PCI)
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PCI_HOST host;
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#endif
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#ifdef DEBUG
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if (bankLength > 0) {
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printf ("mapping bank %d at %08x - %08x\n",
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bankNo, bankBase, bankBase + bankLength - 1);
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} else {
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printf ("unmapping bank %d\n", bankNo);
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}
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#endif
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memoryMapBank (bankNo, bankBase, bankLength);
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#if defined (MAP_PCI) && defined (CONFIG_PCI)
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for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
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const int features =
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PREFETCH_ENABLE |
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DELAYED_READ_ENABLE |
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AGGRESSIVE_PREFETCH |
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READ_LINE_AGGRESSIVE_PREFETCH |
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READ_MULTI_AGGRESSIVE_PREFETCH |
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MAX_BURST_4 | PCI_NO_SWAP;
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pciMapMemoryBank (host, bankNo, bankBase, bankLength);
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pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
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bankLength);
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pciSetRegionFeatures (host, bankNo, features, bankBase,
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bankLength);
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}
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#endif
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return 0;
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}
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'. Some (not all) hardware errors are detected:
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* - short between address lines
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* - short between data lines
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*/
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long int dram_size (long int *base, long int maxsize)
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{
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volatile long int *addr, *b = base;
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long int cnt, val, save1, save2;
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#define STARTVAL (1<<20) /* start test at 1M */
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for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
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cnt <<= 1) {
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addr = base + cnt; /* pointer arith! */
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save1 = *addr; /* save contents of addr */
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save2 = *b; /* save contents of base */
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*addr = cnt; /* write cnt to addr */
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*b = 0; /* put null at base */
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/* check at base address */
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if ((*b) != 0) {
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*addr = save1; /* restore *addr */
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*b = save2; /* restore *b */
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return (0);
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}
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val = *addr; /* read *addr */
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val = *addr; /* read *addr */
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*addr = save1;
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*b = save2;
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if (val != cnt) {
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DP (printf
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("Found %08x at Address %08x (failure)\n",
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(unsigned int) val, (unsigned int) addr));
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/* fix boundary condition.. STARTVAL means zero */
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if (cnt == STARTVAL / sizeof (long))
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cnt = 0;
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return (cnt * sizeof (long));
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}
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}
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return maxsize;
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}
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#define SDRAM_NORMAL 0x0
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#define SDRAM_PRECHARGE_ALL 0x1
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#define SDRAM_REFRESH_ALL 0x2
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#define SDRAM_MODE_REG_SETUP 0x3
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#define SDRAM_XTEN_MODE_REG_SETUP 0x4
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#define SDRAM_NOP 0x5
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#define SDRAM_SELF_REFRESH 0x7
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phys_size_t initdram (int board_type)
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{
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int tmp;
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int start;
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ulong size;
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ulong memSpaceAttr;
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ulong dest;
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/* first disable all banks */
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memory_map_bank(0, 0, 0);
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memory_map_bank(1, 0, 0);
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memory_map_bank(2, 0, 0);
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memory_map_bank(3, 0, 0);
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/* calibrate delay lines */
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set_dfcdlInit();
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GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_NOP); /* 0x1418 */
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do {
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tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
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} while(tmp != 0x0);
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/* SDRAM controller configuration */
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#ifdef CONFIG_MV64460_ECC
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GT_REG_WRITE(MV64460_SDRAM_CONFIG, 0x58201400); /* 0x1400 */
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#else
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GT_REG_WRITE(MV64460_SDRAM_CONFIG, 0x58200400); /* 0x1400 */
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#endif
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GT_REG_WRITE(MV64460_D_UNIT_CONTROL_LOW, 0xC3000540); /* 0x1404 */
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GT_REG_WRITE(MV64460_D_UNIT_CONTROL_HIGH, 0x0300F777); /* 0x1424 */
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GT_REG_WRITE(MV64460_SDRAM_TIMING_CONTROL_LOW, 0x01712220); /* 0x1408 */
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GT_REG_WRITE(MV64460_SDRAM_TIMING_CONTROL_HIGH, 0x0000005D); /* 0x140C */
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GT_REG_WRITE(MV64460_SDRAM_ADDR_CONTROL, 0x00000012); /* 0x1410 */
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GT_REG_WRITE(MV64460_SDRAM_OPEN_PAGES_CONTROL, 0x00000001); /* 0x1414 */
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/* SDRAM drive strength */
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GT_REG_WRITE(MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x80000000); /* 0x14C0 */
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GT_REG_WRITE(MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x80000008); /* 0x14C0 */
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GT_REG_WRITE(MV64460_SDRAM_DATA_PADS_CALIBRATION, 0x80000000); /* 0x14C4 */
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GT_REG_WRITE(MV64460_SDRAM_DATA_PADS_CALIBRATION, 0x80000008); /* 0x14C4 */
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/* setup SDRAM device registers */
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/* precharge all */
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GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_PRECHARGE_ALL); /* 0x1418 */
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do {
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tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
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} while(tmp != 0x0);
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/* enable DLL */
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GT_REG_WRITE(MV64460_EXTENDED_DRAM_MODE, 0x00000000); /* 0x1420 */
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GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_XTEN_MODE_REG_SETUP); /* 0x1418 */
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do {
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tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
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} while(tmp != 0x0);
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/* reset DLL */
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GT_REG_WRITE(MV64460_SDRAM_MODE, 0x00000132); /* 0x141C */
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GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_MODE_REG_SETUP); /* 0x1418 */
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do {
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tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
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} while(tmp != 0x0);
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/* precharge all */
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GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_PRECHARGE_ALL); /* 0x1418 */
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do {
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tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
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} while(tmp != 0x0);
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/* wait for 2 auto refresh commands */
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udelay(20);
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/* un-reset DLL */
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GT_REG_WRITE(MV64460_SDRAM_MODE, 0x00000032); /* 0x141C */
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GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_MODE_REG_SETUP); /* 0x1418 */
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do {
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tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
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} while(tmp != 0x0);
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/* wait 200 cycles */
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udelay(2); /* FIXME make this dynamic for the system clock */
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/* SDRAM init done */
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memory_map_bank(0, CONFIG_SYS_SDRAM_BASE, (256 << 20));
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#ifdef CONFIG_SYS_SDRAM1_BASE
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memory_map_bank(1, CONFIG_SYS_SDRAM1_BASE, (256 << 20));
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#endif
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/* DUNIT_MMASK: enable SnoopHitEn bit to avoid errata CPU-#4
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*/
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tmp = GTREGREAD(MV64460_D_UNIT_MMASK); /* 0x14B0 */
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GT_REG_WRITE(MV64460_D_UNIT_MMASK, tmp | 0x2);
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start = (0 << 20);
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#ifdef CONFIG_P3M750
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size = (512 << 20);
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#elif defined (CONFIG_P3M7448)
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size = (128 << 20);
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#endif
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#ifdef CONFIG_MV64460_ECC
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memSpaceAttr = ((~(BIT0 << 0)) & 0xf) << 8;
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mvDmaSetMemorySpace (0, 0, memSpaceAttr, start, size);
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for (dest = start; dest < start + size; dest += _8M) {
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mvDmaTransfer (0, start, dest, _8M,
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BIT8 /*DMA_DTL_128BYTES */ |
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BIT3 /*DMA_HOLD_SOURCE_ADDR */ |
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BIT11 /*DMA_BLOCK_TRANSFER_MODE */ );
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while (mvDmaIsChannelActive (0));
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}
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#endif
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return (size);
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}
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void board_add_ram_info(int use_default)
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{
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u32 val;
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puts(" (CL=");
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switch ((GTREGREAD(MV64460_SDRAM_MODE) >> 4) & 0x7) {
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case 0x2:
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puts("2");
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break;
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case 0x3:
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puts("3");
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break;
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case 0x5:
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puts("1.5");
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break;
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case 0x6:
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puts("2.5");
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break;
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}
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val = GTREGREAD(MV64460_SDRAM_CONFIG);
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puts(", ECC ");
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if (val & 0x00001000)
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puts("enabled)");
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else
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puts("not enabled)");
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}
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/*
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* mvDmaIsChannelActive - Check if IDMA channel is active
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*
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* channel = IDMA channel number from 0 to 7
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*/
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int mvDmaIsChannelActive (int channel)
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{
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ulong data;
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data = GTREGREAD (MV64460_DMA_CHANNEL0_CONTROL + 4 * channel);
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if (data & BIT14) /* activity status */
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return 1;
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return 0;
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}
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/*
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* mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding
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* map.
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*
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* memSpace = IDMA memory window number from 0 to 7
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* trg_if = Target interface:
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* 0x0 DRAM
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* 0x1 Device Bus
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* 0x2 Integrated SDRAM (or CPU bus 60x only)
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* 0x3 PCI0
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* 0x4 PCI1
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* attr = IDMA attributes (see MV datasheet)
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* base_addr = Sets up memory window for transfers
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*
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*/
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int mvDmaSetMemorySpace (ulong memSpace,
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ulong trg_if,
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ulong attr, ulong base_addr, ulong size)
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{
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ulong temp;
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/* The base address must be aligned to the size. */
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if (base_addr % size != 0)
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return 0;
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if (size >= 0x10000) { /* 64K */
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size &= 0xffff0000;
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base_addr = (base_addr & 0xffff0000);
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/* Set the new attributes */
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GT_REG_WRITE (MV64460_DMA_BASE_ADDR_REG0 + memSpace * 8,
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(base_addr | trg_if | attr));
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GT_REG_WRITE ((MV64460_DMA_SIZE_REG0 + memSpace * 8),
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(size - 1) & 0xffff0000);
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temp = GTREGREAD (MV64460_DMA_BASE_ADDR_ENABLE_REG);
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GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG,
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(temp & ~(BIT0 << memSpace)));
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return 1;
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}
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return 0;
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}
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/*
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* mvDmaTransfer - Transfer data from src_addr to dst_addr on one of the 4
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* DMA channels.
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*
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* channel = IDMA channel number from 0 to 3
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* destAddr = Destination address
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* sourceAddr = Source address
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* size = Size in bytes
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* command = See MV datasheet
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*
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*/
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int mvDmaTransfer (int channel, ulong sourceAddr,
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ulong destAddr, ulong size, ulong command)
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{
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ulong engOffReg = 0; /* Engine Offset Register */
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if (size > 0xffff)
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command = command | BIT31; /* DMA_16M_DESCRIPTOR_MODE */
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command = command | ((command >> 6) & 0x7);
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engOffReg = channel * 4;
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GT_REG_WRITE (MV64460_DMA_CHANNEL0_BYTE_COUNT + engOffReg, size);
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GT_REG_WRITE (MV64460_DMA_CHANNEL0_SOURCE_ADDR + engOffReg, sourceAddr);
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GT_REG_WRITE (MV64460_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg, destAddr);
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command = command |
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BIT12 | /* DMA_CHANNEL_ENABLE */
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BIT9; /* DMA_NON_CHAIN_MODE */
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/* Activate DMA channel By writting to mvDmaControlRegister */
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GT_REG_WRITE (MV64460_DMA_CHANNEL0_CONTROL + engOffReg, command);
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return 1;
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}
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/****************************************************************************************
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* SDRAM INIT *
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* This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb *
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* This procedure fits only the Atlantis *
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* *
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***************************************************************************************/
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/****************************************************************************************
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* DFCDL initialize MV643xx Design Considerations *
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* *
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***************************************************************************************/
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int set_dfcdlInit (void)
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{
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int i;
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/* Values from MV64460 User Manual */
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unsigned int dfcdl_tbl[] = { 0x00000000, 0x00000001, 0x00000042, 0x00000083,
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0x000000c4, 0x00000105, 0x00000146, 0x00000187,
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0x000001c8, 0x00000209, 0x0000024a, 0x0000028b,
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0x000002cc, 0x0000030d, 0x0000034e, 0x0000038f,
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0x000003d0, 0x00000411, 0x00000452, 0x00000493,
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0x000004d4, 0x00000515, 0x00000556, 0x00000597,
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0x000005d8, 0x00000619, 0x0000065a, 0x0000069b,
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0x000006dc, 0x0000071d, 0x0000075e, 0x0000079f,
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0x000007e0, 0x00000821, 0x00000862, 0x000008a3,
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0x000008e4, 0x00000925, 0x00000966, 0x000009a7,
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0x000009e8, 0x00000a29, 0x00000a6a, 0x00000aab,
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0x00000aec, 0x00000b2d, 0x00000b6e, 0x00000baf,
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0x00000bf0, 0x00000c31, 0x00000c72, 0x00000cb3,
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0x00000cf4, 0x00000d35, 0x00000d76, 0x00000db7,
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0x00000df8, 0x00000e39, 0x00000e7a, 0x00000ebb,
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0x00000efc, 0x00000f3d, 0x00000f7e, 0x00000fbf };
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for (i = 0; i < 64; i++)
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GT_REG_WRITE (SRAM_DATA0, dfcdl_tbl[i]);
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GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000); /* enable dynamic delay line updating */
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return (0);
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}
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