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https://github.com/AsahiLinux/u-boot
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e809e74799
The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
123 lines
3.4 KiB
C
123 lines
3.4 KiB
C
/*
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* Copyright 2017 NXP
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* Copyright 2015 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
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#define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
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#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
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#define gur_in32(a) in_le32(a)
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#define gur_out32(a, v) out_le32(a, v)
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#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
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#define gur_in32(a) in_be32(a)
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#define gur_out32(a, v) out_be32(a, v)
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#endif
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#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
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#define scfg_in32(a) in_le32(a)
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#define scfg_out32(a, v) out_le32(a, v)
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#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
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#define scfg_in32(a) in_be32(a)
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#define scfg_out32(a, v) out_be32(a, v)
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#endif
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#ifdef CONFIG_SYS_FSL_PEX_LUT_LE
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#define pex_lut_in32(a) in_le32(a)
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#define pex_lut_out32(a, v) out_le32(a, v)
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#elif defined(CONFIG_SYS_FSL_PEX_LUT_BE)
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#define pex_lut_in32(a) in_be32(a)
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#define pex_lut_out32(a, v) out_be32(a, v)
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#endif
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#ifndef __ASSEMBLY__
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struct cpu_type {
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char name[15];
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u32 soc_ver;
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u32 num_cores;
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};
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#define CPU_TYPE_ENTRY(n, v, nc) \
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{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
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#endif
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#define SVR_WO_E 0xFFFFFE
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#define SVR_LS1012A 0x870400
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#define SVR_LS1043A 0x879200
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#define SVR_LS1023A 0x879208
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#define SVR_LS1046A 0x870700
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#define SVR_LS1026A 0x870708
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#define SVR_LS2045A 0x870120
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#define SVR_LS2080A 0x870110
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#define SVR_LS2085A 0x870100
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#define SVR_LS2040A 0x870130
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#define SVR_LS2088A 0x870900
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#define SVR_LS2084A 0x870910
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#define SVR_LS2048A 0x870920
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#define SVR_LS2044A 0x870930
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#define SVR_LS2081A 0x870919
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#define SVR_LS2041A 0x870915
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#define SVR_DEV_LS2080A 0x8701
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#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
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#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
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#define SVR_REV(svr) (((svr) >> 0) & 0xff)
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#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
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#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
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#define IS_SVR_REV(svr, maj, min) \
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((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
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/* ahci port register default value */
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#define AHCI_PORT_PHY_1_CFG 0xa003fffe
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#define AHCI_PORT_TRANS_CFG 0x08000029
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#define AHCI_PORT_AXICC_CFG 0x3fffffff
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#ifndef __ASSEMBLY__
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/* AHCI (sata) register map */
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struct ccsr_ahci {
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u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
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u32 pcfg; /* port config */
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u32 ppcfg; /* port phy1 config */
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u32 pp2c; /* port phy2 config */
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u32 pp3c; /* port phy3 config */
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u32 pp4c; /* port phy4 config */
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u32 pp5c; /* port phy5 config */
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u32 axicc; /* AXI cache control */
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u32 paxic; /* port AXI config */
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u32 axipc; /* AXI PROT control */
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u32 ptc; /* port Trans Config */
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u32 pts; /* port Trans Status */
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u32 plc; /* port link config */
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u32 plc1; /* port link config1 */
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u32 plc2; /* port link config2 */
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u32 pls; /* port link status */
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u32 pls1; /* port link status1 */
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u32 pcmdc; /* port CMD config */
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u32 ppcs; /* port phy control status */
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u32 pberr; /* port 0/1 BIST error */
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u32 cmds; /* port 0/1 CMD status error */
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};
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#ifdef CONFIG_FSL_LSCH3
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void fsl_lsch3_early_init_f(void);
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#elif defined(CONFIG_FSL_LSCH2)
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void fsl_lsch2_early_init_f(void);
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int setup_chip_volt(void);
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/* Setup core vdd in unit mV */
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int board_setup_core_volt(u32 vdd);
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#endif
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void cpu_name(char *name);
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
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void erratum_a009635(void);
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
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void erratum_a010315(void);
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#endif
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bool soc_has_dp_ddr(void);
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bool soc_has_aiop(void);
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#endif
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#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
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