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https://github.com/AsahiLinux/u-boot
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
214 lines
5.1 KiB
C
214 lines
5.1 KiB
C
/*
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* Copyright (C) 2009 ST-Ericsson SA
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*
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* Adapted from the Linux version:
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* Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* NOTE: This currently does not support the I2C workaround access method.
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*/
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#include <common.h>
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#include <config.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/types.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/arch/prcmu.h>
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/* CPU mailbox registers */
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#define PRCMU_I2C_WRITE(slave) \
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(((slave) << 1) | I2CWRITE | (1 << 6))
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#define PRCMU_I2C_READ(slave) \
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(((slave) << 1) | I2CREAD | (1 << 6))
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#define I2C_MBOX_BIT (1 << 5)
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static int prcmu_is_ready(void)
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{
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int ready = readb(PRCM_XP70_CUR_PWR_STATE) == AP_EXECUTE;
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if (!ready)
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printf("PRCMU firmware not ready\n");
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return ready;
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}
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static int wait_for_i2c_mbx_rdy(void)
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{
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int timeout = 10000;
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if (readl(PRCM_ARM_IT1_VAL) & I2C_MBOX_BIT) {
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printf("prcmu: warning i2c mailbox was not acked\n");
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/* clear mailbox 5 ack irq */
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writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
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}
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/* check any already on-going transaction */
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while ((readl(PRCM_MBOX_CPU_VAL) & I2C_MBOX_BIT) && timeout)
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timeout--;
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if (timeout == 0)
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return -1;
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return 0;
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}
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static int wait_for_i2c_req_done(void)
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{
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int timeout = 10000;
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/* Set an interrupt to XP70 */
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writel(I2C_MBOX_BIT, PRCM_MBOX_CPU_SET);
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/* wait for mailbox 5 (i2c) ack */
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while (!(readl(PRCM_ARM_IT1_VAL) & I2C_MBOX_BIT) && timeout)
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timeout--;
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if (timeout == 0)
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return -1;
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return 0;
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}
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/**
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* prcmu_i2c_read - PRCMU - 4500 communication using PRCMU I2C
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* @reg: - db8500 register bank to be accessed
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* @slave: - db8500 register to be accessed
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* Returns: ACK_MB5 value containing the status
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*/
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int prcmu_i2c_read(u8 reg, u16 slave)
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{
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uint8_t i2c_status;
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uint8_t i2c_val;
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int ret;
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if (!prcmu_is_ready())
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return -1;
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debug("\nprcmu_4500_i2c_read:bank=%x;reg=%x;\n",
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reg, slave);
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ret = wait_for_i2c_mbx_rdy();
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if (ret) {
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printf("prcmu_i2c_read: mailbox became not ready\n");
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return ret;
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}
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/* prepare the data for mailbox 5 */
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writeb(PRCMU_I2C_READ(reg), PRCM_REQ_MB5_I2COPTYPE_REG);
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writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS);
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writeb(slave, PRCM_REQ_MB5_I2CSLAVE);
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writeb(0, PRCM_REQ_MB5_I2CVAL);
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ret = wait_for_i2c_req_done();
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if (ret) {
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printf("prcmu_i2c_read: mailbox request timed out\n");
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return ret;
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}
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/* retrieve values */
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debug("ack-mb5:transfer status = %x\n",
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readb(PRCM_ACK_MB5_STATUS));
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debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1);
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debug("ack-mb5:slave_add = %x\n",
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readb(PRCM_ACK_MB5_SLAVE));
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debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL));
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i2c_status = readb(PRCM_ACK_MB5_STATUS);
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i2c_val = readb(PRCM_ACK_MB5_VAL);
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/* clear mailbox 5 ack irq */
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writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
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if (i2c_status == I2C_RD_OK)
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return i2c_val;
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printf("prcmu_i2c_read:read return status= %d\n", i2c_status);
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return -1;
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}
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/**
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* prcmu_i2c_write - PRCMU-db8500 communication using PRCMU I2C
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* @reg: - db8500 register bank to be accessed
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* @slave: - db800 register to be written to
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* @reg_data: - the data to write
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* Returns: ACK_MB5 value containing the status
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*/
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int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data)
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{
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uint8_t i2c_status;
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int ret;
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if (!prcmu_is_ready())
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return -1;
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debug("\nprcmu_4500_i2c_write:bank=%x;reg=%x;\n",
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reg, slave);
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ret = wait_for_i2c_mbx_rdy();
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if (ret) {
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printf("prcmu_i2c_write: mailbox became not ready\n");
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return ret;
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}
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/* prepare the data for mailbox 5 */
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writeb(PRCMU_I2C_WRITE(reg), PRCM_REQ_MB5_I2COPTYPE_REG);
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writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS);
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writeb(slave, PRCM_REQ_MB5_I2CSLAVE);
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writeb(reg_data, PRCM_REQ_MB5_I2CVAL);
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ret = wait_for_i2c_req_done();
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if (ret) {
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printf("prcmu_i2c_write: mailbox request timed out\n");
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return ret;
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}
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/* retrieve values */
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debug("ack-mb5:transfer status = %x\n",
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readb(PRCM_ACK_MB5_STATUS));
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debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1);
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debug("ack-mb5:slave_add = %x\n",
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readb(PRCM_ACK_MB5_SLAVE));
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debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL));
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i2c_status = readb(PRCM_ACK_MB5_STATUS);
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debug("\ni2c_status = %x\n", i2c_status);
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/* clear mailbox 5 ack irq */
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writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
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if (i2c_status == I2C_WR_OK)
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return 0;
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printf("%s: i2c_status : 0x%x\n", __func__, i2c_status);
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return -1;
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}
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void u8500_prcmu_enable(u32 *reg)
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{
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writel(readl(reg) | (1 << 8), reg);
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}
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void db8500_prcmu_init(void)
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{
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/* Enable timers */
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writel(1 << 17, PRCM_TCR);
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u8500_prcmu_enable((u32 *)PRCM_PER1CLK_MGT_REG);
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u8500_prcmu_enable((u32 *)PRCM_PER2CLK_MGT_REG);
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u8500_prcmu_enable((u32 *)PRCM_PER3CLK_MGT_REG);
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/* PER4CLK does not exist */
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u8500_prcmu_enable((u32 *)PRCM_PER5CLK_MGT_REG);
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u8500_prcmu_enable((u32 *)PRCM_PER6CLK_MGT_REG);
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/* Only exists in ED but is always ok to write to */
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u8500_prcmu_enable((u32 *)PRCM_PER7CLK_MGT_REG);
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u8500_prcmu_enable((u32 *)PRCM_UARTCLK_MGT_REG);
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u8500_prcmu_enable((u32 *)PRCM_I2CCLK_MGT_REG);
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u8500_prcmu_enable((u32 *)PRCM_SDMMCCLK_MGT_REG);
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/* Clean up the mailbox interrupts after pre-u-boot code. */
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writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
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}
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