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https://github.com/AsahiLinux/u-boot
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04b7ce0773
Use common keystone2 Power Sleep controller base address instead of directly deciding which keystone2 SoC is used in psc module. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
233 lines
6.5 KiB
C
233 lines
6.5 KiB
C
/*
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* Keystone: PSC configuration module
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm-generic/errno.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/arch/psc_defs.h>
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#define DEVICE_REG32_R(addr) __raw_readl((u32 *)(addr))
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#define DEVICE_REG32_W(addr, val) __raw_writel(val, (u32 *)(addr))
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int psc_delay(void)
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{
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udelay(10);
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return 10;
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}
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/*
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* FUNCTION PURPOSE: Wait for end of transitional state
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*
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* DESCRIPTION: Polls pstat for the selected domain and waits for transitions
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* to be complete.
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*
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* Since this is boot loader code it is *ASSUMED* that interrupts
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* are disabled and no other core is mucking around with the psc
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* at the same time.
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*
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* Returns 0 when the domain is free. Returns -1 if a timeout
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* occurred waiting for the completion.
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*/
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int psc_wait(u32 domain_num)
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{
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u32 retry;
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u32 ptstat;
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/*
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* Do nothing if the power domain is in transition. This should never
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* happen since the boot code is the only software accesses psc.
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* It's still remotely possible that the hardware state machines
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* initiate transitions.
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* Don't trap if the domain (or a module in this domain) is
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* stuck in transition.
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*/
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retry = 0;
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do {
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ptstat = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PSTAT);
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ptstat = ptstat & (1 << domain_num);
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} while ((ptstat != 0) && ((retry += psc_delay()) <
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PSC_PTSTAT_TIMEOUT_LIMIT));
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if (retry >= PSC_PTSTAT_TIMEOUT_LIMIT)
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return -1;
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return 0;
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}
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u32 psc_get_domain_num(u32 mod_num)
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{
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u32 domain_num;
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/* Get the power domain associated with the module number */
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domain_num = DEVICE_REG32_R(KS2_PSC_BASE +
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PSC_REG_MDCFG(mod_num));
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domain_num = PSC_REG_MDCFG_GET_PD(domain_num);
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return domain_num;
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}
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/*
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* FUNCTION PURPOSE: Power up/down a module
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*
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* DESCRIPTION: Powers up/down the requested module and the associated power
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* domain if required. No action is taken it the module is
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* already powered up/down.
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*
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* This only controls modules. The domain in which the module
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* resides will be left in the power on state. Multiple modules
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* can exist in a power domain, so powering down the domain based
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* on a single module is not done.
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*
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* Returns 0 on success, -1 if the module can't be powered up, or
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* if there is a timeout waiting for the transition.
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*/
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int psc_set_state(u32 mod_num, u32 state)
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{
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u32 domain_num;
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u32 pdctl;
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u32 mdctl;
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u32 ptcmd;
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u32 reset_iso;
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u32 v;
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/*
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* Get the power domain associated with the module number, and reset
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* isolation functionality
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*/
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v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
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domain_num = PSC_REG_MDCFG_GET_PD(v);
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reset_iso = PSC_REG_MDCFG_GET_RESET_ISO(v);
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/* Wait for the status of the domain/module to be non-transitional */
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if (psc_wait(domain_num) != 0)
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return -1;
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/*
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* Perform configuration even if the current status matches the
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* existing state
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*
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* Set the next state of the power domain to on. It's OK if the domain
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* is always on. This code will not ever power down a domain, so no
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* change is made if the new state is power down.
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*/
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if (state == PSC_REG_VAL_MDCTL_NEXT_ON) {
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pdctl = DEVICE_REG32_R(KS2_PSC_BASE +
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PSC_REG_PDCTL(domain_num));
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pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl,
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PSC_REG_VAL_PDCTL_NEXT_ON);
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DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num),
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pdctl);
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}
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/* Set the next state for the module to enabled/disabled */
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mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
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mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state);
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mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso);
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DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
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/* Trigger the enable */
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ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD);
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ptcmd |= (u32)(1<<domain_num);
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DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PTCMD, ptcmd);
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/* Wait on the complete */
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return psc_wait(domain_num);
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}
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/*
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* FUNCTION PURPOSE: Power up a module
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*
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* DESCRIPTION: Powers up the requested module and the associated power domain
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* if required. No action is taken it the module is already
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* powered up.
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*
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* Returns 0 on success, -1 if the module can't be powered up, or
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* if there is a timeout waiting for the transition.
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*/
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int psc_enable_module(u32 mod_num)
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{
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u32 mdctl;
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/* Set the bit to apply reset */
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mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
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if ((mdctl & 0x3f) == PSC_REG_VAL_MDSTAT_STATE_ON)
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return 0;
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return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_ON);
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}
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/*
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* FUNCTION PURPOSE: Power down a module
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*
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* DESCRIPTION: Powers down the requested module.
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*
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* Returns 0 on success, -1 on failure or timeout.
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*/
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int psc_disable_module(u32 mod_num)
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{
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u32 mdctl;
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/* Set the bit to apply reset */
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mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
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if ((mdctl & 0x3f) == 0)
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return 0;
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mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0);
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DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
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return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE);
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}
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/*
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* FUNCTION PURPOSE: Set the reset isolation bit in mdctl
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*
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* DESCRIPTION: The reset isolation enable bit is set. The state of the module
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* is not changed. Returns 0 if the module config showed that
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* reset isolation is supported. Returns 1 otherwise. This is not
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* an error, but setting the bit in mdctl has no effect.
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*/
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int psc_set_reset_iso(u32 mod_num)
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{
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u32 v;
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u32 mdctl;
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/* Set the reset isolation bit */
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mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
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mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, 1);
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DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
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v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
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if (PSC_REG_MDCFG_GET_RESET_ISO(v) == 1)
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return 0;
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return 1;
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}
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/*
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* FUNCTION PURPOSE: Disable a power domain
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*
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* DESCRIPTION: The power domain is disabled
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*/
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int psc_disable_domain(u32 domain_num)
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{
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u32 pdctl;
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u32 ptcmd;
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pdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
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pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, PSC_REG_VAL_PDCTL_NEXT_OFF);
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pdctl = PSC_REG_PDCTL_SET_PDMODE(pdctl, PSC_REG_VAL_PDCTL_PDMODE_SLEEP);
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DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl);
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ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD);
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ptcmd |= (u32)(1 << domain_num);
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DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PTCMD, ptcmd);
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return psc_wait(domain_num);
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}
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