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b5ce63ed12
Added a new function kwgbe_write_hwaddr for programming egiga controller's hardware address. This function will be called for each egiga port being used Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
719 lines
19 KiB
C
719 lines
19 KiB
C
/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* (C) Copyright 2003
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* Ingo Assmus <ingo.assmus@keymile.com>
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*
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* based on - Driver for MV64360X ethernet ports
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* Copyright (C) 2002 rabeeh@galileo.co.il
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <net.h>
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#include <malloc.h>
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#include <miiphy.h>
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#include <asm/errno.h>
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#include <asm/types.h>
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#include <asm/byteorder.h>
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#include <asm/arch/kirkwood.h>
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#include "kirkwood_egiga.h"
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#define KIRKWOOD_PHY_ADR_REQUEST 0xee
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#define KWGBE_SMI_REG (((struct kwgbe_registers *)KW_EGIGA0_BASE)->smi)
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/*
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* smi_reg_read - miiphy_read callback function.
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*
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* Returns 16bit phy register value, or 0xffff on error
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*/
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static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
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{
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struct eth_device *dev = eth_get_dev_by_name(devname);
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struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
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struct kwgbe_registers *regs = dkwgbe->regs;
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u32 smi_reg;
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u32 timeout;
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/* Phyadr read request */
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if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
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reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
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/* */
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*data = (u16) (KWGBEREG_RD(regs->phyadr) & PHYADR_MASK);
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return 0;
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}
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/* check parameters */
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if (phy_adr > PHYADR_MASK) {
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printf("Err..(%s) Invalid PHY address %d\n",
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__FUNCTION__, phy_adr);
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return -EFAULT;
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}
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if (reg_ofs > PHYREG_MASK) {
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printf("Err..(%s) Invalid register offset %d\n",
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__FUNCTION__, reg_ofs);
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return -EFAULT;
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}
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timeout = KWGBE_PHY_SMI_TIMEOUT;
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/* wait till the SMI is not busy */
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do {
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/* read smi register */
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smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
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if (timeout-- == 0) {
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printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
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return -EFAULT;
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}
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} while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
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/* fill the phy address and regiser offset and read opcode */
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smi_reg = (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
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| (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS)
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| KWGBE_PHY_SMI_OPCODE_READ;
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/* write the smi register */
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KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
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/*wait till read value is ready */
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timeout = KWGBE_PHY_SMI_TIMEOUT;
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do {
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/* read smi register */
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smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
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if (timeout-- == 0) {
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printf("Err..(%s) SMI read ready timeout\n",
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__FUNCTION__);
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return -EFAULT;
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}
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} while (!(smi_reg & KWGBE_PHY_SMI_READ_VALID_MASK));
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/* Wait for the data to update in the SMI register */
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for (timeout = 0; timeout < KWGBE_PHY_SMI_TIMEOUT; timeout++) ;
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*data = (u16) (KWGBEREG_RD(KWGBE_SMI_REG) & KWGBE_PHY_SMI_DATA_MASK);
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debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr,
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reg_ofs, *data);
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return 0;
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}
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/*
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* smi_reg_write - imiiphy_write callback function.
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*
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* Returns 0 if write succeed, -EINVAL on bad parameters
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* -ETIME on timeout
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*/
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static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
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{
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struct eth_device *dev = eth_get_dev_by_name(devname);
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struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
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struct kwgbe_registers *regs = dkwgbe->regs;
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u32 smi_reg;
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u32 timeout;
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/* Phyadr write request*/
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if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
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reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
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KWGBEREG_WR(regs->phyadr, data);
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return 0;
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}
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/* check parameters */
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if (phy_adr > PHYADR_MASK) {
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printf("Err..(%s) Invalid phy address\n", __FUNCTION__);
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return -EINVAL;
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}
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if (reg_ofs > PHYREG_MASK) {
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printf("Err..(%s) Invalid register offset\n", __FUNCTION__);
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return -EINVAL;
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}
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/* wait till the SMI is not busy */
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timeout = KWGBE_PHY_SMI_TIMEOUT;
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do {
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/* read smi register */
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smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
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if (timeout-- == 0) {
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printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
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return -ETIME;
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}
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} while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
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/* fill the phy addr and reg offset and write opcode and data */
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smi_reg = (data << KWGBE_PHY_SMI_DATA_OFFS);
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smi_reg |= (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
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| (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS);
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smi_reg &= ~KWGBE_PHY_SMI_OPCODE_READ;
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/* write the smi register */
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KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
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return 0;
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}
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/* Stop and checks all queues */
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static void stop_queue(u32 * qreg)
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{
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u32 reg_data;
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reg_data = readl(qreg);
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if (reg_data & 0xFF) {
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/* Issue stop command for active channels only */
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writel((reg_data << 8), qreg);
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/* Wait for all queue activity to terminate. */
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do {
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/*
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* Check port cause register that all queues
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* are stopped
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*/
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reg_data = readl(qreg);
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}
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while (reg_data & 0xFF);
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}
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}
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/*
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* set_access_control - Config address decode parameters for Ethernet unit
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*
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* This function configures the address decode parameters for the Gigabit
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* Ethernet Controller according the given parameters struct.
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*
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* @regs Register struct pointer.
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* @param Address decode parameter struct.
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*/
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static void set_access_control(struct kwgbe_registers *regs,
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struct kwgbe_winparam *param)
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{
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u32 access_prot_reg;
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/* Set access control register */
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access_prot_reg = KWGBEREG_RD(regs->epap);
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/* clear window permission */
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access_prot_reg &= (~(3 << (param->win * 2)));
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access_prot_reg |= (param->access_ctrl << (param->win * 2));
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KWGBEREG_WR(regs->epap, access_prot_reg);
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/* Set window Size reg (SR) */
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KWGBEREG_WR(regs->barsz[param->win].size,
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(((param->size / 0x10000) - 1) << 16));
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/* Set window Base address reg (BA) */
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KWGBEREG_WR(regs->barsz[param->win].bar,
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(param->target | param->attrib | param->base_addr));
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/* High address remap reg (HARR) */
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if (param->win < 4)
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KWGBEREG_WR(regs->ha_remap[param->win], param->high_addr);
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/* Base address enable reg (BARER) */
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if (param->enable == 1)
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KWGBEREG_BITS_RESET(regs->bare, (1 << param->win));
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else
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KWGBEREG_BITS_SET(regs->bare, (1 << param->win));
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}
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static void set_dram_access(struct kwgbe_registers *regs)
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{
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struct kwgbe_winparam win_param;
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int i;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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/* Set access parameters for DRAM bank i */
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win_param.win = i; /* Use Ethernet window i */
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/* Window target - DDR */
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win_param.target = KWGBE_TARGET_DRAM;
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/* Enable full access */
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win_param.access_ctrl = EWIN_ACCESS_FULL;
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win_param.high_addr = 0;
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/* Get bank base */
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win_param.base_addr = kw_sdram_bar(i);
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win_param.size = kw_sdram_bs(i); /* Get bank size */
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if (win_param.size == 0)
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win_param.enable = 0;
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else
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win_param.enable = 1; /* Enable the access */
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/* Enable DRAM bank */
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switch (i) {
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case 0:
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win_param.attrib = EBAR_DRAM_CS0;
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break;
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case 1:
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win_param.attrib = EBAR_DRAM_CS1;
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break;
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case 2:
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win_param.attrib = EBAR_DRAM_CS2;
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break;
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case 3:
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win_param.attrib = EBAR_DRAM_CS3;
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break;
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default:
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/* invalide bank, disable access */
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win_param.enable = 0;
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win_param.attrib = 0;
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break;
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}
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/* Set the access control for address window(EPAPR) RD/WR */
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set_access_control(regs, &win_param);
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}
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}
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/*
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* port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
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*
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* Go through all the DA filter tables (Unicast, Special Multicast & Other
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* Multicast) and set each entry to 0.
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*/
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static void port_init_mac_tables(struct kwgbe_registers *regs)
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{
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int table_index;
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/* Clear DA filter unicast table (Ex_dFUT) */
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for (table_index = 0; table_index < 4; ++table_index)
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KWGBEREG_WR(regs->dfut[table_index], 0);
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for (table_index = 0; table_index < 64; ++table_index) {
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/* Clear DA filter special multicast table (Ex_dFSMT) */
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KWGBEREG_WR(regs->dfsmt[table_index], 0);
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/* Clear DA filter other multicast table (Ex_dFOMT) */
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KWGBEREG_WR(regs->dfomt[table_index], 0);
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}
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}
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/*
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* port_uc_addr - This function Set the port unicast address table
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*
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* This function locates the proper entry in the Unicast table for the
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* specified MAC nibble and sets its properties according to function
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* parameters.
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* This function add/removes MAC addresses from the port unicast address
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* table.
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*
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* @uc_nibble Unicast MAC Address last nibble.
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* @option 0 = Add, 1 = remove address.
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*
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* RETURN: 1 if output succeeded. 0 if option parameter is invalid.
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*/
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static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
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int option)
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{
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u32 unicast_reg;
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u32 tbl_offset;
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u32 reg_offset;
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/* Locate the Unicast table entry */
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uc_nibble = (0xf & uc_nibble);
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/* Register offset from unicast table base */
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tbl_offset = (uc_nibble / 4);
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/* Entry offset within the above register */
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reg_offset = uc_nibble % 4;
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switch (option) {
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case REJECT_MAC_ADDR:
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/*
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* Clear accepts frame bit at specified unicast
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* DA table entry
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*/
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unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
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unicast_reg &= (0xFF << (8 * reg_offset));
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KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
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break;
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case ACCEPT_MAC_ADDR:
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/* Set accepts frame bit at unicast DA filter table entry */
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unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
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unicast_reg &= (0xFF << (8 * reg_offset));
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unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
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KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
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break;
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default:
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return 0;
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}
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return 1;
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}
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/*
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* port_uc_addr_set - This function Set the port Unicast address.
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*/
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static void port_uc_addr_set(struct kwgbe_registers *regs, u8 * p_addr)
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{
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u32 mac_h;
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u32 mac_l;
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mac_l = (p_addr[4] << 8) | (p_addr[5]);
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mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
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(p_addr[3] << 0);
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KWGBEREG_WR(regs->macal, mac_l);
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KWGBEREG_WR(regs->macah, mac_h);
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/* Accept frames of this address */
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port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
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}
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/*
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* kwgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
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*/
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static void kwgbe_init_rx_desc_ring(struct kwgbe_device *dkwgbe)
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{
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struct kwgbe_rxdesc *p_rx_desc;
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int i;
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/* initialize the Rx descriptors ring */
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p_rx_desc = dkwgbe->p_rxdesc;
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for (i = 0; i < RINGSZ; i++) {
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p_rx_desc->cmd_sts =
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KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
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p_rx_desc->buf_size = PKTSIZE_ALIGN;
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p_rx_desc->byte_cnt = 0;
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p_rx_desc->buf_ptr = dkwgbe->p_rxbuf + i * PKTSIZE_ALIGN;
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if (i == (RINGSZ - 1))
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p_rx_desc->nxtdesc_p = dkwgbe->p_rxdesc;
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else {
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p_rx_desc->nxtdesc_p = (struct kwgbe_rxdesc *)
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((u32) p_rx_desc + KW_RXQ_DESC_ALIGNED_SIZE);
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p_rx_desc = p_rx_desc->nxtdesc_p;
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}
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}
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dkwgbe->p_rxdesc_curr = dkwgbe->p_rxdesc;
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}
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static int kwgbe_init(struct eth_device *dev)
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{
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struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
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struct kwgbe_registers *regs = dkwgbe->regs;
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#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
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&& defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
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int i;
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#endif
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/* setup RX rings */
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kwgbe_init_rx_desc_ring(dkwgbe);
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/* Clear the ethernet port interrupts */
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KWGBEREG_WR(regs->ic, 0);
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KWGBEREG_WR(regs->ice, 0);
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/* Unmask RX buffer and TX end interrupt */
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KWGBEREG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
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/* Unmask phy and link status changes interrupts */
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KWGBEREG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
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set_dram_access(regs);
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port_init_mac_tables(regs);
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port_uc_addr_set(regs, dkwgbe->dev.enetaddr);
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/* Assign port configuration and command. */
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KWGBEREG_WR(regs->pxc, PRT_CFG_VAL);
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KWGBEREG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
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KWGBEREG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
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/* Assign port SDMA configuration */
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KWGBEREG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
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KWGBEREG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
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KWGBEREG_WR(regs->tqx[0].tqxtbc, (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
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/* Turn off the port/RXUQ bandwidth limitation */
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KWGBEREG_WR(regs->pmtu, 0);
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/* Set maximum receive buffer to 9700 bytes */
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KWGBEREG_WR(regs->psc0, KWGBE_MAX_RX_PACKET_9700BYTE
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| (KWGBEREG_RD(regs->psc0) & MRU_MASK));
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/* Enable port initially */
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KWGBEREG_BITS_SET(regs->psc0, KWGBE_SERIAL_PORT_EN);
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/*
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* Set ethernet MTU for leaky bucket mechanism to 0 - this will
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* disable the leaky bucket mechanism .
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*/
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KWGBEREG_WR(regs->pmtu, 0);
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/* Assignment of Rx CRDB of given RXUQ */
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KWGBEREG_WR(regs->rxcdp[RXUQ], (u32) dkwgbe->p_rxdesc_curr);
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/* Enable port Rx. */
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KWGBEREG_WR(regs->rqc, (1 << RXUQ));
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|
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#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
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&& defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
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/* Wait up to 5s for the link status */
|
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for (i = 0; i < 5; i++) {
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u16 phyadr;
|
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|
|
miiphy_read(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
|
|
KIRKWOOD_PHY_ADR_REQUEST, &phyadr);
|
|
/* Return if we get link up */
|
|
if (miiphy_link(dev->name, phyadr))
|
|
return 0;
|
|
udelay(1000000);
|
|
}
|
|
|
|
printf("No link on %s\n", dev->name);
|
|
return -1;
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
static int kwgbe_halt(struct eth_device *dev)
|
|
{
|
|
struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
|
|
struct kwgbe_registers *regs = dkwgbe->regs;
|
|
|
|
/* Disable all gigE address decoder */
|
|
KWGBEREG_WR(regs->bare, 0x3f);
|
|
|
|
stop_queue(®s->tqc);
|
|
stop_queue(®s->rqc);
|
|
|
|
/* Disable port */
|
|
KWGBEREG_BITS_RESET(regs->psc0, KWGBE_SERIAL_PORT_EN);
|
|
/* Set port is not reset */
|
|
KWGBEREG_BITS_RESET(regs->psc1, 1 << 4);
|
|
#ifdef CONFIG_SYS_MII_MODE
|
|
/* Set MMI interface up */
|
|
KWGBEREG_BITS_RESET(regs->psc1, 1 << 3);
|
|
#endif
|
|
/* Disable & mask ethernet port interrupts */
|
|
KWGBEREG_WR(regs->ic, 0);
|
|
KWGBEREG_WR(regs->ice, 0);
|
|
KWGBEREG_WR(regs->pim, 0);
|
|
KWGBEREG_WR(regs->peim, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int kwgbe_write_hwaddr(struct eth_device *dev)
|
|
{
|
|
struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
|
|
struct kwgbe_registers *regs = dkwgbe->regs;
|
|
|
|
/* Programs net device MAC address after initialization */
|
|
port_uc_addr_set(regs, dkwgbe->dev.enetaddr);
|
|
return 0;
|
|
}
|
|
|
|
static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
|
|
int datasize)
|
|
{
|
|
struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
|
|
struct kwgbe_registers *regs = dkwgbe->regs;
|
|
struct kwgbe_txdesc *p_txdesc = dkwgbe->p_txdesc;
|
|
void *p = (void *)dataptr;
|
|
u32 cmd_sts;
|
|
|
|
/* Copy buffer if it's misaligned */
|
|
if ((u32) dataptr & 0x07) {
|
|
if (datasize > PKTSIZE_ALIGN) {
|
|
printf("Non-aligned data too large (%d)\n",
|
|
datasize);
|
|
return -1;
|
|
}
|
|
|
|
memcpy(dkwgbe->p_aligned_txbuf, p, datasize);
|
|
p = dkwgbe->p_aligned_txbuf;
|
|
}
|
|
|
|
p_txdesc->cmd_sts = KWGBE_ZERO_PADDING | KWGBE_GEN_CRC;
|
|
p_txdesc->cmd_sts |= KWGBE_TX_FIRST_DESC | KWGBE_TX_LAST_DESC;
|
|
p_txdesc->cmd_sts |= KWGBE_BUFFER_OWNED_BY_DMA;
|
|
p_txdesc->cmd_sts |= KWGBE_TX_EN_INTERRUPT;
|
|
p_txdesc->buf_ptr = (u8 *) p;
|
|
p_txdesc->byte_cnt = datasize;
|
|
|
|
/* Apply send command using zeroth TXUQ */
|
|
KWGBEREG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc);
|
|
KWGBEREG_WR(regs->tqc, (1 << TXUQ));
|
|
|
|
/*
|
|
* wait for packet xmit completion
|
|
*/
|
|
cmd_sts = readl(&p_txdesc->cmd_sts);
|
|
while (cmd_sts & KWGBE_BUFFER_OWNED_BY_DMA) {
|
|
/* return fail if error is detected */
|
|
if ((cmd_sts & (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME)) ==
|
|
(KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME) &&
|
|
cmd_sts & (KWGBE_UR_ERROR | KWGBE_RL_ERROR)) {
|
|
printf("Err..(%s) in xmit packet\n", __FUNCTION__);
|
|
return -1;
|
|
}
|
|
cmd_sts = readl(&p_txdesc->cmd_sts);
|
|
};
|
|
return 0;
|
|
}
|
|
|
|
static int kwgbe_recv(struct eth_device *dev)
|
|
{
|
|
struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
|
|
struct kwgbe_rxdesc *p_rxdesc_curr = dkwgbe->p_rxdesc_curr;
|
|
u32 cmd_sts;
|
|
u32 timeout = 0;
|
|
|
|
/* wait untill rx packet available or timeout */
|
|
do {
|
|
if (timeout < KWGBE_PHY_SMI_TIMEOUT)
|
|
timeout++;
|
|
else {
|
|
debug("%s time out...\n", __FUNCTION__);
|
|
return -1;
|
|
}
|
|
} while (readl(&p_rxdesc_curr->cmd_sts) & KWGBE_BUFFER_OWNED_BY_DMA);
|
|
|
|
if (p_rxdesc_curr->byte_cnt != 0) {
|
|
debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
|
|
__FUNCTION__, (u32) p_rxdesc_curr->byte_cnt,
|
|
(u32) p_rxdesc_curr->buf_ptr,
|
|
(u32) p_rxdesc_curr->cmd_sts);
|
|
}
|
|
|
|
/*
|
|
* In case received a packet without first/last bits on
|
|
* OR the error summary bit is on,
|
|
* the packets needs to be dropeed.
|
|
*/
|
|
cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
|
|
|
|
if ((cmd_sts &
|
|
(KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC))
|
|
!= (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC)) {
|
|
|
|
printf("Err..(%s) Dropping packet spread on"
|
|
" multiple descriptors\n", __FUNCTION__);
|
|
|
|
} else if (cmd_sts & KWGBE_ERROR_SUMMARY) {
|
|
|
|
printf("Err..(%s) Dropping packet with errors\n",
|
|
__FUNCTION__);
|
|
|
|
} else {
|
|
/* !!! call higher layer processing */
|
|
debug("%s: Sending Received packet to"
|
|
" upper layer (NetReceive)\n", __FUNCTION__);
|
|
|
|
/* let the upper layer handle the packet */
|
|
NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET),
|
|
(int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
|
|
}
|
|
/*
|
|
* free these descriptors and point next in the ring
|
|
*/
|
|
p_rxdesc_curr->cmd_sts =
|
|
KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
|
|
p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
|
|
p_rxdesc_curr->byte_cnt = 0;
|
|
|
|
writel((unsigned)p_rxdesc_curr->nxtdesc_p, (u32) &dkwgbe->p_rxdesc_curr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int kirkwood_egiga_initialize(bd_t * bis)
|
|
{
|
|
struct kwgbe_device *dkwgbe;
|
|
struct eth_device *dev;
|
|
int devnum;
|
|
char *s;
|
|
u8 used_ports[MAX_KWGBE_DEVS] = CONFIG_KIRKWOOD_EGIGA_PORTS;
|
|
|
|
for (devnum = 0; devnum < MAX_KWGBE_DEVS; devnum++) {
|
|
/*skip if port is configured not to use */
|
|
if (used_ports[devnum] == 0)
|
|
continue;
|
|
|
|
if (!(dkwgbe = malloc(sizeof(struct kwgbe_device))))
|
|
goto error1;
|
|
|
|
memset(dkwgbe, 0, sizeof(struct kwgbe_device));
|
|
|
|
if (!(dkwgbe->p_rxdesc =
|
|
(struct kwgbe_rxdesc *)memalign(PKTALIGN,
|
|
KW_RXQ_DESC_ALIGNED_SIZE
|
|
* RINGSZ + 1)))
|
|
goto error2;
|
|
|
|
if (!(dkwgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, RINGSZ
|
|
* PKTSIZE_ALIGN + 1)))
|
|
goto error3;
|
|
|
|
if (!(dkwgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN)))
|
|
goto error4;
|
|
|
|
if (!(dkwgbe->p_txdesc = (struct kwgbe_txdesc *)
|
|
memalign(PKTALIGN, sizeof(struct kwgbe_txdesc) + 1))) {
|
|
free(dkwgbe->p_aligned_txbuf);
|
|
error4:
|
|
free(dkwgbe->p_rxbuf);
|
|
error3:
|
|
free(dkwgbe->p_rxdesc);
|
|
error2:
|
|
free(dkwgbe);
|
|
error1:
|
|
printf("Err.. %s Failed to allocate memory\n",
|
|
__FUNCTION__);
|
|
return -1;
|
|
}
|
|
|
|
dev = &dkwgbe->dev;
|
|
|
|
/* must be less than NAMESIZE (16) */
|
|
sprintf(dev->name, "egiga%d", devnum);
|
|
|
|
/* Extract the MAC address from the environment */
|
|
switch (devnum) {
|
|
case 0:
|
|
dkwgbe->regs = (void *)KW_EGIGA0_BASE;
|
|
s = "ethaddr";
|
|
break;
|
|
case 1:
|
|
dkwgbe->regs = (void *)KW_EGIGA1_BASE;
|
|
s = "eth1addr";
|
|
break;
|
|
default: /* this should never happen */
|
|
printf("Err..(%s) Invalid device number %d\n",
|
|
__FUNCTION__, devnum);
|
|
return -1;
|
|
}
|
|
|
|
while (!eth_getenv_enetaddr(s, dev->enetaddr)) {
|
|
/* Generate Random Private MAC addr if not set */
|
|
dev->enetaddr[0] = 0x02;
|
|
dev->enetaddr[1] = 0x50;
|
|
dev->enetaddr[2] = 0x43;
|
|
dev->enetaddr[3] = get_random_hex();
|
|
dev->enetaddr[4] = get_random_hex();
|
|
dev->enetaddr[5] = get_random_hex();
|
|
eth_setenv_enetaddr(s, dev->enetaddr);
|
|
}
|
|
|
|
dev->init = (void *)kwgbe_init;
|
|
dev->halt = (void *)kwgbe_halt;
|
|
dev->send = (void *)kwgbe_send;
|
|
dev->recv = (void *)kwgbe_recv;
|
|
dev->write_hwaddr = (void *)kwgbe_write_hwaddr;
|
|
|
|
eth_register(dev);
|
|
|
|
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
|
|
miiphy_register(dev->name, smi_reg_read, smi_reg_write);
|
|
/* Set phy address of the port */
|
|
miiphy_write(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
|
|
KIRKWOOD_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
|
|
#endif
|
|
}
|
|
return 0;
|
|
}
|