Jonas Karlman 6da8400d7a clk: rockchip: rk3568: Fix mask for clk_cpll_div_25m_div ... The field for clk_cpll_div_25m_div in CRU_CLKSEL_CON81 is 6 bits wide, not 5 bits wide as currently defined in CPLL_25M_DIV_MASK. Fix this and the assert so that CPLL_25M can be assigned a 25 MHz rate. Fixes: 4a262feba3 ("rockchip: rk3568: add clock driver") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>		2023-08-12 10:35:35 +08:00
..
asm	clk: rockchip: rk3568: Fix mask for clk_cpll_div_25m_div	2023-08-12 10:35:35 +08:00
debug	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00