mirror of
https://github.com/AsahiLinux/u-boot
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e95b61cfb0
Improve PCI access on 32-bits Compact PCI bus Adjust VFD initialization on TRAB Cleanup RRvision video code
49 lines
1.5 KiB
C
49 lines
1.5 KiB
C
/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _PCIPPC2_FPGA_H_
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#define _PCIPPC2_FPGA_H_
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#define FPGA_VENDOR_ID 0x1310
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#define FPGA_DEVICE_ID 0x000d
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#define HW_FPGA0_INT 0x0000
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#define HW_FPGA0_BOARD 0x0060
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#define HW_FPGA0_UART1 0x0080
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#define HW_FPGA0_UART2 0x0100
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#define HW_FPGA0_RTC 0x2000
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#define HW_FPGA0_DOC 0x4000
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#define HW_FPGA1_RTC 0x0000
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#define HW_FPGA1_DOC 0x4000
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#define HW_FPGA0_INT_INTR_MASK 0x30
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#define HW_FPGA0_INT_INTR_STATUS 0x34
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#define HW_FPGA0_INT_INTR_EOI 0x40
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#define HW_FPGA0_INT_SERIAL_CONFIG 0x5c
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#define HW_FPGA0_WDT_CTRL 0x44
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#define HW_FPGA0_WDT_PROG 0x48
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#define HW_FPGA0_WDT_VAL 0x4c
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#define HW_FPGA0_WDT_REFRESH 0x50
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#endif
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