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8991fed97d
We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com>
530 lines
15 KiB
C
530 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
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* Copyright (C) 2018-2019 Rosy Song <rosysong@rosinson.com>
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*/
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <asm/addrspace.h>
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#include <asm/types.h>
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#include <mach/ath79.h>
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#include <mach/ar71xx_regs.h>
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/* QCA956X ETH_SGMII_SERDES Registers */
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#define SGMII_SERDES_RES_CALIBRATION_LSB 23
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#define SGMII_SERDES_RES_CALIBRATION_MASK 0x07800000
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#define SGMII_SERDES_RES_CALIBRATION_SET(x) \
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(((x) << SGMII_SERDES_RES_CALIBRATION_LSB) & SGMII_SERDES_RES_CALIBRATION_MASK)
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#define SGMII_SERDES_CDR_BW_LSB 1
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#define SGMII_SERDES_CDR_BW_MASK 0x00000006
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#define SGMII_SERDES_CDR_BW_SET(x) \
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(((x) << SGMII_SERDES_CDR_BW_LSB) & SGMII_SERDES_CDR_BW_MASK)
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#define SGMII_SERDES_TX_DR_CTRL_LSB 4
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#define SGMII_SERDES_TX_DR_CTRL_MASK 0x00000070
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#define SGMII_SERDES_TX_DR_CTRL_SET(x) \
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(((x) << SGMII_SERDES_TX_DR_CTRL_LSB) & SGMII_SERDES_TX_DR_CTRL_MASK)
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#define SGMII_SERDES_PLL_BW_LSB 8
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#define SGMII_SERDES_PLL_BW_MASK 0x00000100
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#define SGMII_SERDES_PLL_BW_SET(x) \
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(((x) << SGMII_SERDES_PLL_BW_LSB) & SGMII_SERDES_PLL_BW_MASK)
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#define SGMII_SERDES_EN_SIGNAL_DETECT_LSB 16
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#define SGMII_SERDES_EN_SIGNAL_DETECT_MASK 0x00010000
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#define SGMII_SERDES_EN_SIGNAL_DETECT_SET(x) \
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(((x) << SGMII_SERDES_EN_SIGNAL_DETECT_LSB) & SGMII_SERDES_EN_SIGNAL_DETECT_MASK)
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#define SGMII_SERDES_FIBER_SDO_LSB 17
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#define SGMII_SERDES_FIBER_SDO_MASK 0x00020000
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#define SGMII_SERDES_FIBER_SDO_SET(x) \
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(((x) << SGMII_SERDES_FIBER_SDO_LSB) & SGMII_SERDES_FIBER_SDO_MASK)
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#define SGMII_SERDES_VCO_REG_LSB 27
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#define SGMII_SERDES_VCO_REG_MASK 0x78000000
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#define SGMII_SERDES_VCO_REG_SET(x) \
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(((x) << SGMII_SERDES_VCO_REG_LSB) & SGMII_SERDES_VCO_REG_MASK)
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#define SGMII_SERDES_VCO_FAST_LSB 9
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#define SGMII_SERDES_VCO_FAST_MASK 0x00000200
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#define SGMII_SERDES_VCO_FAST_GET(x) \
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(((x) & SGMII_SERDES_VCO_FAST_MASK) >> SGMII_SERDES_VCO_FAST_LSB)
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#define SGMII_SERDES_VCO_SLOW_LSB 10
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#define SGMII_SERDES_VCO_SLOW_MASK 0x00000400
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#define SGMII_SERDES_VCO_SLOW_GET(x) \
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(((x) & SGMII_SERDES_VCO_SLOW_MASK) >> SGMII_SERDES_VCO_SLOW_LSB)
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void _machine_restart(void)
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{
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void __iomem *base;
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u32 reg = 0;
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base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
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MAP_NOCACHE);
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if (soc_is_ar71xx())
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reg = AR71XX_RESET_REG_RESET_MODULE;
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else if (soc_is_ar724x())
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reg = AR724X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar913x())
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reg = AR913X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar933x())
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reg = AR933X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar934x())
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reg = AR934X_RESET_REG_RESET_MODULE;
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else if (soc_is_qca953x())
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reg = QCA953X_RESET_REG_RESET_MODULE;
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else if (soc_is_qca955x())
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reg = QCA955X_RESET_REG_RESET_MODULE;
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else if (soc_is_qca956x())
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reg = QCA956X_RESET_REG_RESET_MODULE;
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else
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puts("Reset register not defined for this SOC\n");
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if (reg)
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setbits_be32(base + reg, AR71XX_RESET_FULL_CHIP);
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while (1)
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/* NOP */;
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}
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u32 ath79_get_bootstrap(void)
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{
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void __iomem *base;
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u32 reg = 0;
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base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
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MAP_NOCACHE);
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if (soc_is_ar933x())
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reg = AR933X_RESET_REG_BOOTSTRAP;
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else if (soc_is_ar934x())
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reg = AR934X_RESET_REG_BOOTSTRAP;
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else if (soc_is_qca953x())
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reg = QCA953X_RESET_REG_BOOTSTRAP;
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else if (soc_is_qca955x())
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reg = QCA955X_RESET_REG_BOOTSTRAP;
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else if (soc_is_qca956x())
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reg = QCA956X_RESET_REG_BOOTSTRAP;
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else
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puts("Bootstrap register not defined for this SOC\n");
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if (reg)
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return readl(base + reg);
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return 0;
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}
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static int eth_init_ar933x(void)
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{
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void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
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MAP_NOCACHE);
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void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
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MAP_NOCACHE);
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void __iomem *gregs = map_physmem(AR933X_GMAC_BASE, AR933X_GMAC_SIZE,
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MAP_NOCACHE);
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const u32 mask = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO |
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AR933X_RESET_GE1_MAC | AR933X_RESET_GE1_MDIO |
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AR933X_RESET_ETH_SWITCH |
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AR933X_RESET_ETH_SWITCH_ANALOG;
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/* Clear MDIO slave EN bit. */
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clrbits_be32(rregs + AR933X_RESET_REG_BOOTSTRAP, BIT(17));
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mdelay(10);
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/* Get Atheros S26 PHY out of reset. */
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clrsetbits_be32(pregs + AR933X_PLL_SWITCH_CLOCK_CONTROL_REG,
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0x1f, 0x10);
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mdelay(10);
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setbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask);
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mdelay(10);
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clrbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask);
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mdelay(10);
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/* Configure AR93xx GMAC register. */
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clrsetbits_be32(gregs + AR933X_GMAC_REG_ETH_CFG,
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AR933X_ETH_CFG_MII_GE0_MASTER |
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AR933X_ETH_CFG_MII_GE0_SLAVE,
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AR933X_ETH_CFG_MII_GE0_SLAVE);
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return 0;
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}
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static int eth_init_ar934x(void)
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{
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void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
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MAP_NOCACHE);
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void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
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MAP_NOCACHE);
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void __iomem *gregs = map_physmem(AR934X_GMAC_BASE, AR934X_GMAC_SIZE,
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MAP_NOCACHE);
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const u32 mask = AR934X_RESET_GE0_MAC | AR934X_RESET_GE0_MDIO |
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AR934X_RESET_GE1_MAC | AR934X_RESET_GE1_MDIO |
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AR934X_RESET_ETH_SWITCH_ANALOG;
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u32 reg;
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reg = readl(rregs + AR934X_RESET_REG_BOOTSTRAP);
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if (reg & AR934X_BOOTSTRAP_REF_CLK_40)
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writel(0x570, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
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else
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writel(0x271, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
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writel(BIT(26) | BIT(25), pregs + AR934X_PLL_ETH_XMII_CONTROL_REG);
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setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
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mdelay(1);
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clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
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mdelay(1);
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/* Configure AR934x GMAC register. */
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writel(AR934X_ETH_CFG_RGMII_GMAC0, gregs + AR934X_GMAC_REG_ETH_CFG);
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return 0;
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}
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static int eth_init_qca953x(void)
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{
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void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
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MAP_NOCACHE);
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const u32 mask = QCA953X_RESET_GE0_MAC | QCA953X_RESET_GE0_MDIO |
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QCA953X_RESET_GE1_MAC | QCA953X_RESET_GE1_MDIO |
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QCA953X_RESET_ETH_SWITCH_ANALOG |
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QCA953X_RESET_ETH_SWITCH;
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setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
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mdelay(1);
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clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
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mdelay(1);
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return 0;
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}
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static int qca956x_sgmii_cal(void)
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{
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int i;
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u32 reg, rev_sgmii_val;
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u32 vco_fast, vco_slow;
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u32 start_val = 0, end_val = 0;
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void __iomem *gregs = map_physmem(AR71XX_MII_BASE, AR71XX_MII_SIZE,
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MAP_NOCACHE);
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void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
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MAP_NOCACHE);
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void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
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MAP_NOCACHE);
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const u32 mask = QCA956X_RESET_SGMII_ASSERT | QCA956X_RESET_SGMII;
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writel(BIT(2) | BIT(0), pregs + QCA956X_PLL_ETH_SGMII_SERDES_REG);
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reg = readl(gregs + QCA956X_GMAC_REG_SGMII_SERDES);
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vco_fast = SGMII_SERDES_VCO_FAST_GET(reg);
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vco_slow = SGMII_SERDES_VCO_SLOW_GET(reg);
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/* Set resistor calibration from 0000 to 1111 */
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for (i = 0; i < 0x10; i++) {
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reg = (readl(gregs + QCA956X_GMAC_REG_SGMII_SERDES) &
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~SGMII_SERDES_RES_CALIBRATION_MASK) |
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SGMII_SERDES_RES_CALIBRATION_SET(i);
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writel(reg, gregs + QCA956X_GMAC_REG_SGMII_SERDES);
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udelay(50);
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reg = readl(gregs + QCA956X_GMAC_REG_SGMII_SERDES);
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if (vco_fast != SGMII_SERDES_VCO_FAST_GET(reg) ||
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vco_slow != SGMII_SERDES_VCO_SLOW_GET(reg)) {
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if (start_val == 0) {
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start_val = i;
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end_val = i;
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} else {
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end_val = i;
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}
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}
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vco_fast = SGMII_SERDES_VCO_FAST_GET(reg);
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vco_slow = SGMII_SERDES_VCO_SLOW_GET(reg);
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}
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if (start_val == 0)
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rev_sgmii_val = 0x7;
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else
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rev_sgmii_val = (start_val + end_val) >> 1;
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writel((readl(gregs + QCA956X_GMAC_REG_SGMII_SERDES) &
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~SGMII_SERDES_RES_CALIBRATION_MASK) |
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SGMII_SERDES_RES_CALIBRATION_SET(rev_sgmii_val),
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gregs + QCA956X_GMAC_REG_SGMII_SERDES);
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writel(BIT(2) | BIT(0), pregs + QCA956X_PLL_ETH_SGMII_SERDES_REG);
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reg = readl(gregs + QCA956X_GMAC_REG_SGMII_SERDES);
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writel(SGMII_SERDES_CDR_BW_SET(3) | SGMII_SERDES_TX_DR_CTRL_SET(1) |
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SGMII_SERDES_PLL_BW_SET(1) | SGMII_SERDES_EN_SIGNAL_DETECT_SET(1) |
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SGMII_SERDES_FIBER_SDO_SET(1) | SGMII_SERDES_VCO_REG_SET(3) | reg,
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gregs + QCA956X_GMAC_REG_SGMII_SERDES);
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setbits_be32(rregs + QCA956X_RESET_REG_RESET_MODULE, mask);
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mdelay(1);
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clrbits_be32(rregs + QCA956X_RESET_REG_RESET_MODULE, mask);
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mdelay(1);
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while (!(readl(gregs + QCA956X_GMAC_REG_SGMII_SERDES) & BIT(15)))
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/* NOP */;
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return 0;
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}
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static int qca956x_sgmii_setup(void)
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{
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int i;
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u32 s = 0, reg = 0;
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u32 _regs[] = {
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BIT(4), /* HW_RX_125M_N */
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BIT(2), /* RX_125M_N */
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BIT(3), /* TX_125M_N */
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BIT(0), /* RX_CLK_N */
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BIT(1), /* TX_CLK_N */
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};
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void __iomem *gregs = map_physmem(AR71XX_MII_BASE, AR71XX_MII_SIZE,
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MAP_NOCACHE);
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/* Force sgmii mode */
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writel(BIT(6) | BIT(15) | BIT(8), gregs + QCA956X_GMAC_REG_MR_AN_CTRL);
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udelay(10);
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writel(0x2 | BIT(5) | (0x2 << 6), gregs + QCA956X_GMAC_REG_SGMII_CONFIG);
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/* SGMII reset sequence sugguest by qca systems team. */
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writel(0, gregs + QCA956X_GMAC_REG_SGMII_RESET);
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for (i = 0; i < ARRAY_SIZE(_regs); i++) {
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reg |= _regs[i];
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writel(reg, gregs + QCA956X_GMAC_REG_SGMII_RESET);
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}
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writel(readl(gregs + QCA956X_GMAC_REG_MR_AN_CTRL) & ~BIT(15),
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gregs + QCA956X_GMAC_REG_MR_AN_CTRL);
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/*
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* WARNING: Across resets SGMII link status goes to weird state.
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* if 0xb8070058 (SGMII_DEBUG Register) reads other than 0xf or 0x10
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* for sure we are in bad state.
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* Issue a PHY RESET in MR_AN_CONTROL_ADDRESS to keep going.
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*/
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i = 0;
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s = (readl(gregs + QCA956X_GMAC_REG_SGMII_DEBUG) & 0xff);
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while (!(s == 0xf || s == 0x10)) {
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writel(readl(gregs + QCA956X_GMAC_REG_MR_AN_CTRL) | BIT(15),
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gregs + QCA956X_GMAC_REG_MR_AN_CTRL);
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udelay(100);
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writel(readl(gregs + QCA956X_GMAC_REG_MR_AN_CTRL) & ~BIT(15),
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gregs + QCA956X_GMAC_REG_MR_AN_CTRL);
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if (i++ == 10)
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break;
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s = (readl(gregs + QCA956X_GMAC_REG_SGMII_DEBUG) & 0xff);
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}
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return 0;
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}
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static int qca956x_s17_reset(void)
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{
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void __iomem *regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
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MAP_NOCACHE);
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void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
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MAP_NOCACHE);
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const u32 mask = QCA956X_RESET_SGMII_ASSERT | QCA956X_RESET_SGMII |
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QCA956X_RESET_EXTERNAL | QCA956X_RESET_SGMII_ANALOG |
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QCA956X_RESET_SWITCH;
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/* Bits(Reserved in datasheet) should be set to 1 */
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const u32 mask_r = QCA956X_RESET_SGMII_ASSERT | QCA956X_RESET_SGMII |
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QCA956X_RESET_EXTERNAL;
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setbits_be32(rregs + QCA956X_RESET_REG_RESET_MODULE, mask);
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mdelay(1);
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clrbits_be32(rregs + QCA956X_RESET_REG_RESET_MODULE, mask_r);
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mdelay(1);
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/* Reset s17 switch(GPIO11) SYS_RST_L */
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writel(readl(regs + AR71XX_GPIO_REG_OE) & ~BIT(11),
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regs + AR71XX_GPIO_REG_OE);
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udelay(100);
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writel(readl(regs + AR71XX_GPIO_REG_OUT) & ~BIT(11),
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regs + AR71XX_GPIO_REG_OUT);
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udelay(100);
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writel(readl(regs + AR71XX_GPIO_REG_OUT) | BIT(11),
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regs + AR71XX_GPIO_REG_OUT);
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return 0;
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}
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static int qca956x_init_mdio(void)
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{
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u32 reg;
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void __iomem *regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
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MAP_NOCACHE);
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void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
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MAP_NOCACHE);
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const u32 mask = QCA956X_RESET_GE0_MDIO | QCA956X_RESET_GE0_MAC |
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QCA956X_RESET_GE1_MDIO | QCA956X_RESET_GE1_MAC;
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setbits_be32(rregs + QCA956X_RESET_REG_RESET_MODULE, mask);
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mdelay(1);
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clrbits_be32(rregs + QCA956X_RESET_REG_RESET_MODULE, mask);
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mdelay(1);
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/* GPIO4 as MDI */
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reg = readl(regs + QCA956X_GPIO_REG_IN_ENABLE3);
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reg &= ~(0xff << 16);
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reg |= (0x4 << 16);
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writel(reg, regs + QCA956X_GPIO_REG_IN_ENABLE3);
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/* GPIO4 as MDO */
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reg = readl(regs + QCA956X_GPIO_REG_OUT_FUNC1);
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reg &= ~0xff;
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reg |= 0x20;
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writel(reg, regs + QCA956X_GPIO_REG_OUT_FUNC1);
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/* Init MDC(GPIO3) / MDIO(GPIO4) */
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reg = readl(regs + AR71XX_GPIO_REG_OE);
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reg &= ~BIT(4);
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writel(reg, regs + AR71XX_GPIO_REG_OE);
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udelay(100);
|
|
|
|
reg = readl(regs + AR71XX_GPIO_REG_OE);
|
|
reg &= ~BIT(3);
|
|
writel(reg, regs + AR71XX_GPIO_REG_OE);
|
|
udelay(100);
|
|
|
|
/* GPIO3 as MDI */
|
|
reg = readl(regs + QCA956X_GPIO_REG_OUT_FUNC0);
|
|
reg &= ~(0xff << 24);
|
|
reg |= (0x21 << 24);
|
|
writel(reg, regs + QCA956X_GPIO_REG_OUT_FUNC0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int eth_init_qca956x(void)
|
|
{
|
|
void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
|
|
MAP_NOCACHE);
|
|
void __iomem *gregs = map_physmem(AR71XX_MII_BASE, AR71XX_MII_SIZE,
|
|
MAP_NOCACHE);
|
|
|
|
qca956x_sgmii_cal();
|
|
qca956x_s17_reset();
|
|
qca956x_init_mdio();
|
|
|
|
if (ath79_get_bootstrap() & QCA956X_BOOTSTRAP_REF_CLK_40)
|
|
writel(0x45500, pregs + QCA956X_PLL_SWITCH_CLK_CTRL_REG);
|
|
else
|
|
writel(0xc5200, pregs + QCA956X_PLL_SWITCH_CLK_CTRL_REG);
|
|
|
|
qca956x_sgmii_setup();
|
|
|
|
writel((3 << 16) | (3 << 14) | (1 << 0) | (1 << 6),
|
|
gregs + QCA956X_GMAC_REG_ETH_CFG);
|
|
|
|
writel((1 << 31) | (2 << 28) | (2 << 26) | (1 << 25),
|
|
pregs + QCA956X_PLL_ETH_XMII_CTRL_REG);
|
|
mdelay(1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int ath79_eth_reset(void)
|
|
{
|
|
/*
|
|
* Un-reset ethernet. DM still doesn't have any notion of reset
|
|
* framework, so we do it by hand here.
|
|
*/
|
|
if (soc_is_ar933x())
|
|
return eth_init_ar933x();
|
|
if (soc_is_ar934x())
|
|
return eth_init_ar934x();
|
|
if (soc_is_qca953x())
|
|
return eth_init_qca953x();
|
|
if (soc_is_qca956x())
|
|
return eth_init_qca956x();
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int usb_reset_ar933x(void __iomem *reset_regs)
|
|
{
|
|
/* Ungate the USB block */
|
|
setbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
|
|
AR933X_RESET_USBSUS_OVERRIDE);
|
|
mdelay(1);
|
|
clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
|
|
AR933X_RESET_USB_HOST);
|
|
mdelay(1);
|
|
clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
|
|
AR933X_RESET_USB_PHY);
|
|
mdelay(1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int usb_reset_ar934x(void __iomem *reset_regs)
|
|
{
|
|
/* Ungate the USB block */
|
|
setbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
|
|
AR934X_RESET_USBSUS_OVERRIDE);
|
|
mdelay(1);
|
|
clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
|
|
AR934X_RESET_USB_PHY);
|
|
mdelay(1);
|
|
clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
|
|
AR934X_RESET_USB_PHY_ANALOG);
|
|
mdelay(1);
|
|
clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
|
|
AR934X_RESET_USB_HOST);
|
|
mdelay(1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int usb_reset_qca953x(void __iomem *reset_regs)
|
|
{
|
|
void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
|
|
MAP_NOCACHE);
|
|
|
|
clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
|
|
0xf00, 0x200);
|
|
mdelay(10);
|
|
|
|
/* Ungate the USB block */
|
|
setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
|
|
QCA953X_RESET_USBSUS_OVERRIDE);
|
|
mdelay(1);
|
|
clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
|
|
QCA953X_RESET_USB_PHY);
|
|
mdelay(1);
|
|
clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
|
|
QCA953X_RESET_USB_PHY_ANALOG);
|
|
mdelay(1);
|
|
clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
|
|
QCA953X_RESET_USB_HOST);
|
|
mdelay(1);
|
|
clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
|
|
QCA953X_RESET_USB_PHY_PLL_PWD_EXT);
|
|
mdelay(1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int ath79_usb_reset(void)
|
|
{
|
|
void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
|
|
AR71XX_USB_CTRL_SIZE,
|
|
MAP_NOCACHE);
|
|
void __iomem *reset_regs = map_physmem(AR71XX_RESET_BASE,
|
|
AR71XX_RESET_SIZE,
|
|
MAP_NOCACHE);
|
|
/*
|
|
* Turn on the Buff and Desc swap bits.
|
|
* NOTE: This write into an undocumented register in mandatory to
|
|
* get the USB controller operational in BigEndian mode.
|
|
*/
|
|
writel(0xf0000, usbc_regs + AR71XX_USB_CTRL_REG_CONFIG);
|
|
|
|
if (soc_is_ar933x())
|
|
return usb_reset_ar933x(reset_regs);
|
|
if (soc_is_ar934x())
|
|
return usb_reset_ar934x(reset_regs);
|
|
if (soc_is_qca953x())
|
|
return usb_reset_qca953x(reset_regs);
|
|
|
|
return -EINVAL;
|
|
}
|