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https://github.com/AsahiLinux/u-boot
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174d728471
Update my and DPs email address to match current setup. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
65 lines
1.1 KiB
Text
65 lines
1.1 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for Xilinx Versal Mini eMMC0 Configuration
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*
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* (C) Copyright 2018-2019, Xilinx, Inc.
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*
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* Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
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* Michal Simek <michal.simek@amd.com>
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*/
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/dts-v1/;
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/ {
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compatible = "xlnx,versal";
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#address-cells = <2>;
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#size-cells = <2>;
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model = "Xilinx Versal MINI eMMC0";
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clk200: clk200 {
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compatible = "fixed-clock";
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#clock-cells = <0x0>;
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clock-frequency = <200000000>;
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};
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dcc: dcc {
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compatible = "arm,dcc";
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status = "okay";
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bootph-all;
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};
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amba: amba {
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bootph-all;
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compatible = "simple-bus";
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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ranges;
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sdhci0: sdhci@f1040000 {
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compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
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status = "okay";
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non-removable;
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disable-wp;
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bus-width = <8>;
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reg = <0x0 0xf1040000 0x0 0x10000>;
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&clk200 &clk200>;
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no-1-8-v;
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xlnx,mio-bank = <0>;
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};
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};
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aliases {
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serial0 = &dcc;
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mmc0 = &sdhci0;
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};
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chosen {
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stdout-path = "serial0:115200";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x20000000>;
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};
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};
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