mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 17:07:38 +00:00
9f603e2fff
Device tree alignment with kernel v6.0-rc4. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
417 lines
12 KiB
Text
417 lines
12 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
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*
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*/
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#include <dt-bindings/pinctrl/stm32-pinfunc.h>
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#include <dt-bindings/mfd/stm32f4-rcc.h>
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/ {
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soc {
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pinctrl: pinctrl@40020000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x40020000 0x3000>;
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interrupt-parent = <&exti>;
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st,syscfg = <&syscfg 0x8>;
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pins-are-numbered;
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gpioa: gpio@40020000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x0 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
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st,bank-name = "GPIOA";
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};
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gpiob: gpio@40020400 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x400 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
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st,bank-name = "GPIOB";
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};
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gpioc: gpio@40020800 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x800 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
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st,bank-name = "GPIOC";
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};
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gpiod: gpio@40020c00 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0xc00 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
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st,bank-name = "GPIOD";
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};
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gpioe: gpio@40021000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1000 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
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st,bank-name = "GPIOE";
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};
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gpiof: gpio@40021400 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1400 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
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st,bank-name = "GPIOF";
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};
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gpiog: gpio@40021800 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1800 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
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st,bank-name = "GPIOG";
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};
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gpioh: gpio@40021c00 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1c00 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
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st,bank-name = "GPIOH";
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};
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gpioi: gpio@40022000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x2000 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
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st,bank-name = "GPIOI";
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};
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gpioj: gpio@40022400 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x2400 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
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st,bank-name = "GPIOJ";
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};
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gpiok: gpio@40022800 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x2800 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
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st,bank-name = "GPIOK";
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};
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usart1_pins_a: usart1-0 {
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pins1 {
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pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
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bias-disable;
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};
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};
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usart3_pins_a: usart3-0 {
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pins1 {
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pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
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bias-disable;
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};
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};
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usbotg_fs_pins_a: usbotg-fs-0 {
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pins {
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pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
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<STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
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<STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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};
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};
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usbotg_fs_pins_b: usbotg-fs-1 {
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pins {
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pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */
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<STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */
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<STM32_PINMUX('B', 15, AF12)>; /* OTG_HS_DP */
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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};
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};
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usbotg_hs_pins_a: usbotg-hs-0 {
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pins {
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pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT*/
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<STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
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<STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
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<STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
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<STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
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<STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
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<STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
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<STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
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<STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
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<STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
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<STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
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<STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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};
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};
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ethernet_mii: mii-0 {
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pins {
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pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */
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<STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */
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<STM32_PINMUX('C', 2, AF11)>, /* ETH_MII_TXD2 */
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<STM32_PINMUX('B', 8, AF11)>, /* ETH_MII_TXD3 */
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<STM32_PINMUX('C', 3, AF11)>, /* ETH_MII_TX_CLK */
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<STM32_PINMUX('G', 11,AF11)>, /* ETH_MII_TX_EN_ETH_RMII_TX_EN */
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<STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
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<STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
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<STM32_PINMUX('A', 1, AF11)>, /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */
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<STM32_PINMUX('A', 7, AF11)>, /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */
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<STM32_PINMUX('C', 4, AF11)>, /* ETH_MII_RXD0_ETH_RMII_RXD0 */
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<STM32_PINMUX('C', 5, AF11)>, /* ETH_MII_RXD1_ETH_RMII_RXD1 */
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<STM32_PINMUX('H', 6, AF11)>, /* ETH_MII_RXD2 */
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<STM32_PINMUX('H', 7, AF11)>; /* ETH_MII_RXD3 */
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slew-rate = <2>;
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};
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};
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adc3_in8_pin: adc-200 {
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pins {
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pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
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};
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};
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pwm1_pins: pwm1-0 {
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pins {
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pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */
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<STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */
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<STM32_PINMUX('B', 12, AF1)>; /* TIM1_BKIN */
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};
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};
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pwm3_pins: pwm3-0 {
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pins {
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pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */
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<STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
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};
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};
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i2c1_pins: i2c1-0 {
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pins {
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pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */
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<STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */
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bias-disable;
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drive-open-drain;
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slew-rate = <3>;
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};
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};
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ltdc_pins_a: ltdc-0 {
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pins {
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pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
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<STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
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<STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
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<STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
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<STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
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<STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
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<STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
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<STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
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<STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
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<STM32_PINMUX('J', 5, AF14)>, /* LCD_R6*/
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<STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
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<STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
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<STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
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<STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
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<STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
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<STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
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<STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
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<STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
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<STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
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<STM32_PINMUX('J', 15, AF14)>, /* LCD_B3*/
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<STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
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<STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
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<STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
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<STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
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<STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
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<STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
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<STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */
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<STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */
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slew-rate = <2>;
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};
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};
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ltdc_pins_b: ltdc-1 {
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pins {
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pinmux = <STM32_PINMUX('C', 6, AF14)>,
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/* LCD_HSYNC */
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<STM32_PINMUX('A', 4, AF14)>,
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/* LCD_VSYNC */
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<STM32_PINMUX('G', 7, AF14)>,
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/* LCD_CLK */
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<STM32_PINMUX('C', 10, AF14)>,
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/* LCD_R2 */
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<STM32_PINMUX('B', 0, AF9)>,
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/* LCD_R3 */
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<STM32_PINMUX('A', 11, AF14)>,
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/* LCD_R4 */
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<STM32_PINMUX('A', 12, AF14)>,
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/* LCD_R5 */
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<STM32_PINMUX('B', 1, AF9)>,
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/* LCD_R6*/
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<STM32_PINMUX('G', 6, AF14)>,
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/* LCD_R7 */
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<STM32_PINMUX('A', 6, AF14)>,
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/* LCD_G2 */
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<STM32_PINMUX('G', 10, AF9)>,
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/* LCD_G3 */
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<STM32_PINMUX('B', 10, AF14)>,
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/* LCD_G4 */
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<STM32_PINMUX('D', 6, AF14)>,
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/* LCD_B2 */
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<STM32_PINMUX('G', 11, AF14)>,
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/* LCD_B3*/
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<STM32_PINMUX('B', 11, AF14)>,
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/* LCD_G5 */
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<STM32_PINMUX('C', 7, AF14)>,
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/* LCD_G6 */
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<STM32_PINMUX('D', 3, AF14)>,
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/* LCD_G7 */
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<STM32_PINMUX('G', 12, AF9)>,
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/* LCD_B4 */
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<STM32_PINMUX('A', 3, AF14)>,
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/* LCD_B5 */
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<STM32_PINMUX('B', 8, AF14)>,
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/* LCD_B6 */
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<STM32_PINMUX('B', 9, AF14)>,
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/* LCD_B7 */
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<STM32_PINMUX('F', 10, AF14)>;
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/* LCD_DE */
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slew-rate = <2>;
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};
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};
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spi5_pins: spi5-0 {
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pins1 {
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pinmux = <STM32_PINMUX('F', 7, AF5)>,
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/* SPI5_CLK */
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<STM32_PINMUX('F', 9, AF5)>;
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/* SPI5_MOSI */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('F', 8, AF5)>;
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/* SPI5_MISO */
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bias-disable;
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};
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};
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i2c3_pins: i2c3-0 {
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pins {
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pinmux = <STM32_PINMUX('C', 9, AF4)>,
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/* I2C3_SDA */
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<STM32_PINMUX('A', 8, AF4)>;
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/* I2C3_SCL */
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bias-disable;
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drive-open-drain;
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slew-rate = <3>;
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};
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};
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dcmi_pins: dcmi-0 {
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pins {
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pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */
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<STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */
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<STM32_PINMUX('A', 6, AF13)>, /* DCMI_PIXCLK */
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<STM32_PINMUX('C', 6, AF13)>, /* DCMI_D0 */
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<STM32_PINMUX('C', 7, AF13)>, /* DCMI_D1 */
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<STM32_PINMUX('C', 8, AF13)>, /* DCMI_D2 */
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<STM32_PINMUX('C', 9, AF13)>, /* DCMI_D3 */
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<STM32_PINMUX('C', 11, AF13)>, /*DCMI_D4 */
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<STM32_PINMUX('D', 3, AF13)>, /* DCMI_D5 */
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<STM32_PINMUX('B', 8, AF13)>, /* DCMI_D6 */
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<STM32_PINMUX('E', 6, AF13)>, /* DCMI_D7 */
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<STM32_PINMUX('C', 10, AF13)>, /* DCMI_D8 */
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<STM32_PINMUX('C', 12, AF13)>, /* DCMI_D9 */
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<STM32_PINMUX('D', 6, AF13)>, /* DCMI_D10 */
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<STM32_PINMUX('D', 2, AF13)>; /* DCMI_D11 */
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bias-disable;
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drive-push-pull;
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slew-rate = <3>;
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};
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};
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sdio_pins: sdio-pins-0 {
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pins {
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pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
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<STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
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<STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
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<STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
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<STM32_PINMUX('C', 12, AF12)>, /* SDIO_CK */
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<STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
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drive-push-pull;
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slew-rate = <2>;
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};
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};
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sdio_pins_od: sdio-pins-od-0 {
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pins1 {
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pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
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<STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
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<STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
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<STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
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<STM32_PINMUX('C', 12, AF12)>; /* SDIO_CK */
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drive-push-pull;
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slew-rate = <2>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
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drive-open-drain;
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slew-rate = <2>;
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};
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};
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};
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};
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};
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