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https://github.com/AsahiLinux/u-boot
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e3e01a6f94
The Renesas RZ/G2L SMARC Evaluation Board Kit consists of the RZ/G2L System-on-Module (SOM) based on the R9A07G044L2 SoC, and a common SMARC carrier board. This patch is based on the corresponding Linux v6.5 device tree (commit 52e12027d50affbf60c6c9c64db8017391b0c22e). Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
353 lines
7.8 KiB
Text
353 lines
7.8 KiB
Text
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the RZ/{G2L,V2L} SMARC SOM common parts
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
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#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
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/* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
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#define EMMC 1
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/*
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* To enable uSD card on CN3,
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* SW1[2] should be at position 3/ON.
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* Disable eMMC by setting "#define EMMC 0" above.
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*/
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#define SDHI (!EMMC)
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/ {
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aliases {
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ethernet0 = ð0;
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ethernet1 = ð1;
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};
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chosen {
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bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
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};
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memory@48000000 {
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device_type = "memory";
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/* first 128MB is reserved for secure area. */
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reg = <0x0 0x48000000 0x0 0x78000000>;
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_1p1v: regulator-vdd-core {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.1V";
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1100000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vccq_sdhi0: regulator-vccq-sdhi0 {
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compatible = "regulator-gpio";
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regulator-name = "SDHI0 VccQ";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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states = <3300000 1>, <1800000 0>;
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regulator-boot-on;
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gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
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regulator-always-on;
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};
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};
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&adc {
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pinctrl-0 = <&adc_pins>;
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pinctrl-names = "default";
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status = "okay";
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/delete-node/ channel@6;
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/delete-node/ channel@7;
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};
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ð0 {
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pinctrl-0 = <ð0_pins>;
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pinctrl-names = "default";
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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status = "okay";
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phy0: ethernet-phy@7 {
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compatible = "ethernet-phy-id0022.1640",
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"ethernet-phy-ieee802.3-c22";
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reg = <7>;
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interrupt-parent = <&irqc>;
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interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
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rxc-skew-psec = <2400>;
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txc-skew-psec = <2400>;
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rxdv-skew-psec = <0>;
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txdv-skew-psec = <0>;
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rxd0-skew-psec = <0>;
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rxd1-skew-psec = <0>;
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rxd2-skew-psec = <0>;
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rxd3-skew-psec = <0>;
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txd0-skew-psec = <0>;
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txd1-skew-psec = <0>;
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txd2-skew-psec = <0>;
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txd3-skew-psec = <0>;
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};
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};
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ð1 {
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pinctrl-0 = <ð1_pins>;
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pinctrl-names = "default";
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phy-handle = <&phy1>;
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phy-mode = "rgmii-id";
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status = "okay";
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phy1: ethernet-phy@7 {
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compatible = "ethernet-phy-id0022.1640",
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"ethernet-phy-ieee802.3-c22";
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reg = <7>;
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interrupt-parent = <&irqc>;
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interrupts = <RZG2L_IRQ3 IRQ_TYPE_LEVEL_LOW>;
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rxc-skew-psec = <2400>;
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txc-skew-psec = <2400>;
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rxdv-skew-psec = <0>;
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txdv-skew-psec = <0>;
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rxd0-skew-psec = <0>;
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rxd1-skew-psec = <0>;
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rxd2-skew-psec = <0>;
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rxd3-skew-psec = <0>;
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txd0-skew-psec = <0>;
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txd1-skew-psec = <0>;
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txd2-skew-psec = <0>;
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txd3-skew-psec = <0>;
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};
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};
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&extal_clk {
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clock-frequency = <24000000>;
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};
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&gpu {
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mali-supply = <®_1p1v>;
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};
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&ostm1 {
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status = "okay";
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};
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&ostm2 {
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status = "okay";
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};
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&pinctrl {
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adc_pins: adc {
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pinmux = <RZG2L_PORT_PINMUX(9, 0, 2)>; /* ADC_TRG */
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};
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eth0_pins: eth0 {
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pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
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<RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
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<RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
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<RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
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<RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
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<RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
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<RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
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<RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
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<RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
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<RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
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<RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
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<RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
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<RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
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<RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
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<RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */
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<RZG2L_PORT_PINMUX(1, 0, 1)>; /* IRQ2 */
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};
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eth1_pins: eth1 {
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pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
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<RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
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<RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
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<RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
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<RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
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<RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
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<RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
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<RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
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<RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
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<RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
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<RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
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<RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
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<RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
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<RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
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<RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */
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<RZG2L_PORT_PINMUX(1, 1, 1)>; /* IRQ3 */
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};
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gpio-sd0-pwr-en-hog {
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gpio-hog;
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gpios = <RZG2L_GPIO(4, 1) GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "gpio_sd0_pwr_en";
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};
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qspi0_pins: qspi0 {
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qspi0-data {
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pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
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power-source = <1800>;
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};
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qspi0-ctrl {
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pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
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power-source = <1800>;
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};
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};
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/*
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* SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
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* The below switch logic can be used to select the device between
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* eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
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* SW1[2] should be at position 2/OFF to enable 64 GB eMMC
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* SW1[2] should be at position 3/ON to enable uSD card CN3
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*/
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sd0-dev-sel-hog {
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gpio-hog;
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gpios = <RZG2L_GPIO(41, 1) GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "sd0_dev_sel";
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};
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sdhi0_emmc_pins: sd0emmc {
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sd0_emmc_data {
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pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
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"SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
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power-source = <1800>;
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};
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sd0_emmc_ctrl {
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pins = "SD0_CLK", "SD0_CMD";
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power-source = <1800>;
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};
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sd0_emmc_rst {
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pins = "SD0_RST#";
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power-source = <1800>;
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};
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};
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sdhi0_pins: sd0 {
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sd0_data {
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pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
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power-source = <3300>;
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};
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sd0_ctrl {
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pins = "SD0_CLK", "SD0_CMD";
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power-source = <3300>;
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};
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sd0_mux {
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pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
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};
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};
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sdhi0_pins_uhs: sd0_uhs {
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sd0_data_uhs {
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pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
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power-source = <1800>;
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};
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sd0_ctrl_uhs {
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pins = "SD0_CLK", "SD0_CMD";
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power-source = <1800>;
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};
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sd0_mux_uhs {
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pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
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};
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};
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};
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&sbc {
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pinctrl-0 = <&qspi0_pins>;
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pinctrl-names = "default";
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status = "okay";
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flash@0 {
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compatible = "micron,mt25qu512a", "jedec,spi-nor";
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reg = <0>;
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m25p,fast-read;
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spi-max-frequency = <50000000>;
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spi-rx-bus-width = <4>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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boot@0 {
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reg = <0x00000000 0x2000000>;
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read-only;
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};
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user@2000000 {
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reg = <0x2000000 0x2000000>;
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};
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};
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};
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};
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#if SDHI
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&sdhi0 {
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pinctrl-0 = <&sdhi0_pins>;
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pinctrl-1 = <&sdhi0_pins_uhs>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <&vccq_sdhi0>;
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bus-width = <4>;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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status = "okay";
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};
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#endif
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#if EMMC
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&sdhi0 {
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pinctrl-0 = <&sdhi0_emmc_pins>;
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pinctrl-1 = <&sdhi0_emmc_pins>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_1p8v>;
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bus-width = <8>;
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mmc-hs200-1_8v;
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non-removable;
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fixed-emmc-driver-type = <1>;
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status = "okay";
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};
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#endif
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&wdt0 {
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status = "okay";
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timeout-sec = <60>;
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};
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&wdt1 {
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status = "okay";
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timeout-sec = <60>;
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};
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