mirror of
https://github.com/AsahiLinux/u-boot
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35c4bccd89
Distinguish more clearly between source files meant for producing .dtb from those meant for producing .dtbo. No functional change, as we currently have rules for producing a foo.dtbo from either foo.dts or foo.dtso. Note that in the linux tree, all device tree overlay sources have been renamed to .dtso, and the .dts->.dtbo rule is gone since v6.5 (commit 81d362732bac). So this is also a step towards staying closer to linux with respect to both Kbuild and device tree sources. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Jan Kiszka <jan.kiszka@siemens.com>
47 lines
1,001 B
Text
47 lines
1,001 B
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* IOT2050 M.2 variant, overlay for B-key USB3.0 + E-key PCIE1_LANE0
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* Copyright (c) Siemens AG, 2022
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*
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* Authors:
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* Chao Zeng <chao.zeng@siemens.com>
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* Jan Kiszka <jan.kiszka@siemens.com>
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/gpio/gpio.h>
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&serdes0 {
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assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
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};
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&pcie0_rc {
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status = "disabled";
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};
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&pcie1_rc {
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pinctrl-names = "default";
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pinctrl-0 = <&minipcie_pins_default>;
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num-lanes = <1>;
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phys = <&serdes1 PHY_TYPE_PCIE 0>;
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phy-names = "pcie-phy0";
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reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&dwc3_0 {
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assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
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<&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */
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phys = <&serdes0 PHY_TYPE_USB3 0>;
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phy-names = "usb3-phy";
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};
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&usb0 {
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maximum-speed = "super-speed";
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snps,dis-u1-entry-quirk;
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snps,dis-u2-entry-quirk;
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};
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