mirror of
https://github.com/AsahiLinux/u-boot
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09f3ca3dd5
We have finished Generic Board conversion for ARM and PowerPC, i.e. all the boards have been converted except OpenRISC, SuperH, SPARC, which have not supported Generic Board framework yet. Select SYS_GENERIC_BOARD in arch/Kconfig and delete all the macro defines in include/configs/*.h. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
290 lines
7 KiB
C
290 lines
7 KiB
C
/*
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* (C) Copyright 2012
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* Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
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* Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_DISPLAY_BOARDINFO
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/* KMBEC FPGA (PRIO) */
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#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
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#define CONFIG_SYS_KMBEC_FPGA_SIZE 64
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#if defined CONFIG_KMETER1
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#define CONFIG_HOSTNAME kmeter1
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#define CONFIG_KM_BOARD_NAME "kmeter1"
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#define CONFIG_KM_DEF_NETDEV "netdev=eth2\0"
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#elif defined CONFIG_KMCOGE5NE
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#define CONFIG_HOSTNAME kmcoge5ne
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#define CONFIG_KM_BOARD_NAME "kmcoge5ne"
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#define CONFIG_KM_DEF_NETDEV "netdev=eth1\0"
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#define CONFIG_CMD_NAND
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#define CONFIG_NAND_ECC_BCH
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#define CONFIG_BCH
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#define CONFIG_NAND_KMETER1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
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#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
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#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
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#define MTDIDS_DEFAULT "nor0=boot,nand0=app"
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#define MTDPARTS_DEFAULT "mtdparts=" \
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"boot:" \
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"768k(u-boot)," \
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"128k(env)," \
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"128k(envred)," \
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"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" \
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"app:" \
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"-(" CONFIG_KM_UBI_PARTITION_NAME_APP ");"
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#else
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#error ("Board not supported")
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#endif
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_QE /* Has QE */
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#define CONFIG_MPC8360 /* MPC8360 CPU specific */
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#define CONFIG_SYS_TEXT_BASE 0xF0000000
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/* include common defines/options for all 83xx Keymile boards */
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#include "km/km83xx-common.h"
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/*
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* System IO Setup
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*/
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#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
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/*
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* Hardware Reset Configuration Word
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*/
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#define CONFIG_SYS_HRCW_LOW (\
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HRCWL_CSB_TO_CLKIN_4X1 | \
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HRCWL_CORE_TO_CSB_2X1 | \
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HRCWL_CE_PLL_VCO_DIV_2 | \
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HRCWL_CE_TO_PLL_1X6)
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#define CONFIG_SYS_HRCW_HIGH (\
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HRCWH_CORE_ENABLE | \
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HRCWH_FROM_0X00000100 | \
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HRCWH_BOOTSEQ_DISABLE | \
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HRCWH_SW_WATCHDOG_DISABLE | \
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HRCWH_ROM_LOC_LOCAL_16BIT | \
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HRCWH_BIG_ENDIAN | \
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HRCWH_LALE_EARLY | \
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HRCWH_LDP_CLEAR)
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/**
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* DDR RAM settings
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*/
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#define CONFIG_SYS_DDR_SDRAM_CFG (\
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SDRAM_CFG_SDRAM_TYPE_DDR2 | \
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SDRAM_CFG_SREN | \
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SDRAM_CFG_HSE)
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#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
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#ifdef CONFIG_KMCOGE5NE
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/**
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* KMCOGE5NE has 512 MB RAM
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*/
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#define CONFIG_SYS_DDR_CS0_CONFIG (\
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CSCONFIG_EN | \
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CSCONFIG_AP | \
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CSCONFIG_ODT_RD_ONLY_CURRENT | \
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CSCONFIG_BANK_BIT_3 | \
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CSCONFIG_ROW_BIT_13 | \
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CSCONFIG_COL_BIT_10)
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#else
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#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
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CSCONFIG_ROW_BIT_13 | \
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CSCONFIG_COL_BIT_10 | \
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CSCONFIG_ODT_RD_ONLY_CURRENT)
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#endif
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#define CONFIG_SYS_DDR_CLK_CNTL (\
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DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
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#define CONFIG_SYS_DDR_INTERVAL (\
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(0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
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(0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
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#define CONFIG_SYS_DDRCDR (\
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DDRCDR_EN | \
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DDRCDR_Q_DRN)
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#define CONFIG_SYS_DDR_MODE 0x47860452
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#define CONFIG_SYS_DDR_MODE2 0x8080c000
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#define CONFIG_SYS_DDR_TIMING_0 (\
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(2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
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(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
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(6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
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(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
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(0 << TIMING_CFG0_WWT_SHIFT) | \
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(0 << TIMING_CFG0_RRT_SHIFT) | \
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(0 << TIMING_CFG0_WRT_SHIFT) | \
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(0 << TIMING_CFG0_RWT_SHIFT))
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#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
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(2 << TIMING_CFG1_WRTORD_SHIFT) | \
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(2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
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(3 << TIMING_CFG1_WRREC_SHIFT) | \
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(7 << TIMING_CFG1_REFREC_SHIFT) | \
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(3 << TIMING_CFG1_ACTTORW_SHIFT) | \
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(8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
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(3 << TIMING_CFG1_PRETOACT_SHIFT))
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#define CONFIG_SYS_DDR_TIMING_2 (\
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(0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
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(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
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(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
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(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
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(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
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(5 << TIMING_CFG2_CPO_SHIFT) | \
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(0 << TIMING_CFG2_ADD_LAT_SHIFT))
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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/* EEprom support */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
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#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2
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#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
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/*
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* PAXE on the local bus CS3
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*/
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#define CONFIG_SYS_PAXE_BASE 0xA0000000
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#define CONFIG_SYS_PAXE_SIZE 256
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#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE
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#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */
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#define CONFIG_SYS_BR3_PRELIM (\
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CONFIG_SYS_PAXE_BASE | \
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(1 << BR_PS_SHIFT) | \
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BR_V)
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#define CONFIG_SYS_OR3_PRELIM (\
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MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
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OR_GPCM_CSNT | \
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OR_GPCM_ACS_DIV2 | \
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OR_GPCM_SCY_2 | \
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OR_GPCM_TRLX | \
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OR_GPCM_EAD)
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#ifdef CONFIG_KMCOGE5NE
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/*
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* BFTIC3 on the local bus CS4
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*/
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#define CONFIG_SYS_BFTIC3_BASE 0xB0000000
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#define CONFIG_SYS_BFTIC3_SIZE 256
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#define CONFIG_SYS_BR4_PRELIM (\
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CONFIG_SYS_BFTIC3_BASE |\
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(1 << BR_PS_SHIFT) | \
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BR_V)
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#define CONFIG_SYS_OR4_PRELIM (\
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MEG_TO_AM(CONFIG_SYS_BFTIC3_SIZE) |\
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OR_GPCM_CSNT | \
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OR_GPCM_ACS_DIV2 |\
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OR_GPCM_SCY_2 |\
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OR_GPCM_TRLX |\
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OR_GPCM_EAD)
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#endif
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/*
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* MMU Setup
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*/
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/* PAXE: icache cacheable, but dcache-inhibit and guarded */
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#define CONFIG_SYS_IBAT5L (\
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CONFIG_SYS_PAXE_BASE | \
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BATL_PP_10 | \
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BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT5U (\
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CONFIG_SYS_PAXE_BASE | \
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BATU_BL_256M | \
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BATU_VS | \
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BATU_VP)
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#define CONFIG_SYS_DBAT5L (\
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CONFIG_SYS_PAXE_BASE | \
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BATL_PP_10 | \
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BATL_CACHEINHIBIT | \
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BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
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#ifdef CONFIG_KMCOGE5NE
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/* BFTIC3: icache cacheable, but dcache-inhibit and guarded */
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#define CONFIG_SYS_IBAT6L (\
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CONFIG_SYS_BFTIC3_BASE | \
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BATL_PP_10 | \
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BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT6U (\
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CONFIG_SYS_BFTIC3_BASE | \
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BATU_BL_256M | \
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BATU_VS | \
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BATU_VP)
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#define CONFIG_SYS_DBAT6L (\
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CONFIG_SYS_BFTIC3_BASE | \
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BATL_PP_10 | \
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BATL_CACHEINHIBIT | \
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BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
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/* DDR/LBC SDRAM next 256M: cacheable */
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#define CONFIG_SYS_IBAT7L (\
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CONFIG_SYS_SDRAM_BASE2 |\
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BATL_PP_10 |\
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BATL_CACHEINHIBIT |\
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BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT7U (\
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CONFIG_SYS_SDRAM_BASE2 |\
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BATU_BL_256M |\
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BATU_VS |\
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BATU_VP)
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/* enable POST tests */
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#define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS)
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#define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */
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#define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END
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#define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */
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#define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */
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#define CONFIG_CMD_DIAG /* so that testpin is inquired for POST test */
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#else
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#define CONFIG_SYS_IBAT6L (0)
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#define CONFIG_SYS_IBAT6U (0)
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#define CONFIG_SYS_IBAT7L (0)
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#define CONFIG_SYS_IBAT7U (0)
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#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
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#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
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#endif
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#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
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#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
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#endif /* CONFIG */
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