mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-12 14:23:00 +00:00
67ddd56251
DT node pic@40000 is defined explicitly in p2020-post.dtsi file and also transitionally via include file pq3-mpic.dtsi. Remove duplicate definition from p2020-post.dtsi. No change in final DTB file. Signed-off-by: Pali Rohár <pali@kernel.org>
197 lines
4.2 KiB
Text
197 lines
4.2 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
|
/*
|
|
* P2020 Silicon/SoC Device Tree Source (post include)
|
|
*
|
|
* Copyright 2013 Freescale Semiconductor Inc.
|
|
* Copyright 2019 NXP
|
|
*/
|
|
|
|
&soc {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
device_type = "soc";
|
|
compatible = "fsl,p2020-immr", "simple-bus";
|
|
bus-frequency = <0x0>;
|
|
|
|
ecm-law@0 {
|
|
compatible = "fsl,ecm-law";
|
|
reg = <0x0 0x1000>;
|
|
fsl,num-laws = <12>;
|
|
};
|
|
|
|
ecm@1000 {
|
|
compatible = "fsl,p2020-ecm", "fsl,ecm";
|
|
reg = <0x1000 0x1000>;
|
|
interrupts = <17 2 0 0>;
|
|
};
|
|
|
|
memory-controller@2000 {
|
|
compatible = "fsl,p2020-memory-controller";
|
|
reg = <0x2000 0x1000>;
|
|
interrupts = <18 2 0 0>;
|
|
};
|
|
|
|
/include/ "pq3-i2c-0.dtsi"
|
|
/include/ "pq3-i2c-1.dtsi"
|
|
/include/ "pq3-duart-0.dtsi"
|
|
|
|
espi0: spi@7000 {
|
|
compatible = "fsl,mpc8536-espi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x7000 0x1000>;
|
|
interrupts = < 0x3b 0x02 0x00 0x00 >;
|
|
fsl,espi-num-chipselects = <4>;
|
|
};
|
|
|
|
/include/ "pq3-dma-1.dtsi"
|
|
/include/ "pq3-gpio-0.dtsi"
|
|
|
|
L2: l2-cache-controller@20000 {
|
|
compatible = "fsl,p2020-l2-cache-controller";
|
|
reg = <0x20000 0x1000>;
|
|
cache-line-size = <32>; /* 32 bytes */
|
|
cache-size = <0x80000>; /* L2,512K */
|
|
interrupts = <16 2 0 0>;
|
|
};
|
|
|
|
/include/ "pq3-dma-0.dtsi"
|
|
|
|
usb@22000 {
|
|
compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
|
|
reg = <0x22000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <28 0x2 0 0>;
|
|
phy_type = "ulpi";
|
|
};
|
|
|
|
/include/ "pq3-etsec1-0.dtsi"
|
|
/include/ "pq3-etsec1-timer-0.dtsi"
|
|
|
|
ptp_clock@24e00 {
|
|
interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>;
|
|
};
|
|
|
|
/include/ "pq3-etsec1-1.dtsi"
|
|
/include/ "pq3-etsec1-2.dtsi"
|
|
|
|
esdhc: sdhc@2e000 {
|
|
compatible = "fsl,p2020-esdhc", "fsl,esdhc";
|
|
reg = <0x2e000 0x1000>;
|
|
interrupts = <72 0x2 0 0>;
|
|
/* Filled in by U-Boot */
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
/include/ "pq3-sec3.1-0.dtsi"
|
|
/include/ "pq3-mpic.dtsi"
|
|
/include/ "pq3-mpic-timer-B.dtsi"
|
|
|
|
global-utilities@e0000 {
|
|
compatible = "fsl,p2020-guts";
|
|
reg = <0xe0000 0x1000>;
|
|
fsl,has-rstcr;
|
|
};
|
|
|
|
pmc: power@e0070 {
|
|
compatible = "fsl,mpc8548-pmc";
|
|
reg = <0xe0070 0x20>;
|
|
};
|
|
};
|
|
|
|
/* PCIe controller base address 0x8000 */
|
|
&pci2 {
|
|
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie";
|
|
law_trgt_if = <0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
bus-range = <0x0 0xff>;
|
|
clock-frequency = <33333333>;
|
|
interrupts = <24 2 0 0>;
|
|
|
|
pcie@0 {
|
|
reg = <0 0 0 0 0>;
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
device_type = "pci";
|
|
interrupts = <24 2 0 0>;
|
|
interrupt-map-mask = <0xf800 0 0 7>;
|
|
|
|
interrupt-map = <
|
|
/* IDSEL 0x0 */
|
|
0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
|
|
0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
|
|
0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
|
|
0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
|
|
>;
|
|
};
|
|
};
|
|
|
|
/* PCIe controller base address 0x9000 */
|
|
&pci1 {
|
|
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie";
|
|
law_trgt_if = <1>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
bus-range = <0x0 0xff>;
|
|
clock-frequency = <33333333>;
|
|
interrupts = <25 2 0 0>;
|
|
|
|
pcie@0 {
|
|
reg = <0 0 0 0 0>;
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
device_type = "pci";
|
|
interrupts = <25 2 0 0>;
|
|
interrupt-map-mask = <0xf800 0 0 7>;
|
|
|
|
interrupt-map = <
|
|
/* IDSEL 0x0 */
|
|
0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
|
|
0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
|
|
0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
|
|
0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
|
|
>;
|
|
};
|
|
};
|
|
|
|
/* PCIe controller base address 0xa000 */
|
|
&pci0 {
|
|
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie";
|
|
law_trgt_if = <2>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
bus-range = <0x0 0xff>;
|
|
clock-frequency = <33333333>;
|
|
interrupts = <26 2 0 0>;
|
|
|
|
pcie@0 {
|
|
reg = <0 0 0 0 0>;
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
device_type = "pci";
|
|
interrupts = <26 2 0 0>;
|
|
interrupt-map-mask = <0xf800 0 0 7>;
|
|
interrupt-map = <
|
|
/* IDSEL 0x0 */
|
|
0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
|
|
0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
|
|
0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
|
|
0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
|
|
>;
|
|
};
|
|
};
|
|
|
|
&lbc {
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
|
|
interrupts = <19 2 0 0>;
|
|
};
|