mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-08 14:14:32 +00:00
bae4e8cb92
i.MX8QM does not share same FUSE MAC word index, so update the word index for i.MX8QM. Signed-off-by: Peng Fan <peng.fan@nxp.com>
537 lines
11 KiB
C
537 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*/
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#include <common.h>
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#include <clk.h>
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#include <cpu.h>
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#include <dm.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <dm/uclass.h>
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#include <errno.h>
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#include <thermal.h>
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#include <asm/arch/sci/sci.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch-imx/cpu.h>
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#include <asm/armv8/cpu.h>
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#include <asm/armv8/mmu.h>
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#include <asm/mach-imx/boot_mode.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define BT_PASSOVER_TAG 0x504F
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struct pass_over_info_t *get_pass_over_info(void)
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{
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struct pass_over_info_t *p =
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(struct pass_over_info_t *)PASS_OVER_INFO_ADDR;
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if (p->barker != BT_PASSOVER_TAG ||
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p->len != sizeof(struct pass_over_info_t))
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return NULL;
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return p;
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}
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int arch_cpu_init(void)
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{
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#ifdef CONFIG_SPL_BUILD
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struct pass_over_info_t *pass_over;
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if (is_soc_rev(CHIP_REV_A)) {
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pass_over = get_pass_over_info();
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if (pass_over && pass_over->g_ap_mu == 0) {
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/*
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* When ap_mu is 0, means the U-Boot booted
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* from first container
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*/
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sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
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}
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}
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#endif
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return 0;
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}
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int arch_cpu_init_dm(void)
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{
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struct udevice *devp;
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int node, ret;
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node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu");
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ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
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if (ret) {
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printf("could not get scu %d\n", ret);
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return ret;
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}
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if (is_imx8qm()) {
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ret = sc_pm_set_resource_power_mode(-1, SC_R_SMMU,
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SC_PM_PW_MODE_ON);
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if (ret)
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return ret;
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}
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return 0;
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}
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int print_bootinfo(void)
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{
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enum boot_device bt_dev = get_boot_device();
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puts("Boot: ");
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switch (bt_dev) {
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case SD1_BOOT:
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puts("SD0\n");
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break;
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case SD2_BOOT:
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puts("SD1\n");
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break;
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case SD3_BOOT:
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puts("SD2\n");
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break;
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case MMC1_BOOT:
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puts("MMC0\n");
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break;
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case MMC2_BOOT:
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puts("MMC1\n");
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break;
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case MMC3_BOOT:
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puts("MMC2\n");
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break;
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case FLEXSPI_BOOT:
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puts("FLEXSPI\n");
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break;
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case SATA_BOOT:
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puts("SATA\n");
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break;
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case NAND_BOOT:
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puts("NAND\n");
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break;
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case USB_BOOT:
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puts("USB\n");
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break;
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default:
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printf("Unknown device %u\n", bt_dev);
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break;
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}
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return 0;
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}
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enum boot_device get_boot_device(void)
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{
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enum boot_device boot_dev = SD1_BOOT;
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sc_rsrc_t dev_rsrc;
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sc_misc_get_boot_dev(-1, &dev_rsrc);
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switch (dev_rsrc) {
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case SC_R_SDHC_0:
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boot_dev = MMC1_BOOT;
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break;
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case SC_R_SDHC_1:
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boot_dev = SD2_BOOT;
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break;
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case SC_R_SDHC_2:
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boot_dev = SD3_BOOT;
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break;
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case SC_R_NAND:
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boot_dev = NAND_BOOT;
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break;
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case SC_R_FSPI_0:
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boot_dev = FLEXSPI_BOOT;
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break;
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case SC_R_SATA_0:
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boot_dev = SATA_BOOT;
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break;
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case SC_R_USB_0:
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case SC_R_USB_1:
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case SC_R_USB_2:
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boot_dev = USB_BOOT;
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break;
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default:
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break;
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}
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return boot_dev;
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}
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#ifdef CONFIG_ENV_IS_IN_MMC
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__weak int board_mmc_get_env_dev(int devno)
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{
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return CONFIG_SYS_MMC_ENV_DEV;
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}
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int mmc_get_env_dev(void)
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{
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sc_rsrc_t dev_rsrc;
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int devno;
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sc_misc_get_boot_dev(-1, &dev_rsrc);
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switch (dev_rsrc) {
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case SC_R_SDHC_0:
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devno = 0;
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break;
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case SC_R_SDHC_1:
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devno = 1;
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break;
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case SC_R_SDHC_2:
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devno = 2;
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break;
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default:
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/* If not boot from sd/mmc, use default value */
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return CONFIG_SYS_MMC_ENV_DEV;
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}
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return board_mmc_get_env_dev(devno);
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}
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#endif
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#define MEMSTART_ALIGNMENT SZ_2M /* Align the memory start with 2MB */
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static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start,
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sc_faddr_t *addr_end)
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{
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sc_faddr_t start, end;
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int ret;
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bool owned;
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owned = sc_rm_is_memreg_owned(-1, mr);
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if (owned) {
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ret = sc_rm_get_memreg_info(-1, mr, &start, &end);
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if (ret) {
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printf("Memreg get info failed, %d\n", ret);
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return -EINVAL;
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}
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debug("0x%llx -- 0x%llx\n", start, end);
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*addr_start = start;
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*addr_end = end;
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return 0;
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}
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return -EINVAL;
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}
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phys_size_t get_effective_memsize(void)
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{
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sc_rm_mr_t mr;
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sc_faddr_t start, end, end1;
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int err;
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end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
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for (mr = 0; mr < 64; mr++) {
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err = get_owned_memreg(mr, &start, &end);
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if (!err) {
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start = roundup(start, MEMSTART_ALIGNMENT);
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/* Too small memory region, not use it */
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if (start > end)
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continue;
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/* Find the memory region runs the U-Boot */
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if (start >= PHYS_SDRAM_1 && start <= end1 &&
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(start <= CONFIG_SYS_TEXT_BASE &&
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end >= CONFIG_SYS_TEXT_BASE)) {
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if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 +
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PHYS_SDRAM_1_SIZE))
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return (end - PHYS_SDRAM_1 + 1);
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else
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return PHYS_SDRAM_1_SIZE;
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}
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}
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}
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return PHYS_SDRAM_1_SIZE;
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}
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int dram_init(void)
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{
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sc_rm_mr_t mr;
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sc_faddr_t start, end, end1, end2;
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int err;
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end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
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end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
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for (mr = 0; mr < 64; mr++) {
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err = get_owned_memreg(mr, &start, &end);
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if (!err) {
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start = roundup(start, MEMSTART_ALIGNMENT);
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/* Too small memory region, not use it */
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if (start > end)
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continue;
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if (start >= PHYS_SDRAM_1 && start <= end1) {
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if ((end + 1) <= end1)
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gd->ram_size += end - start + 1;
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else
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gd->ram_size += end1 - start;
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} else if (start >= PHYS_SDRAM_2 && start <= end2) {
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if ((end + 1) <= end2)
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gd->ram_size += end - start + 1;
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else
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gd->ram_size += end2 - start;
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}
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}
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}
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/* If error, set to the default value */
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if (!gd->ram_size) {
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gd->ram_size = PHYS_SDRAM_1_SIZE;
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gd->ram_size += PHYS_SDRAM_2_SIZE;
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}
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return 0;
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}
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static void dram_bank_sort(int current_bank)
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{
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phys_addr_t start;
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phys_size_t size;
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while (current_bank > 0) {
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if (gd->bd->bi_dram[current_bank - 1].start >
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gd->bd->bi_dram[current_bank].start) {
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start = gd->bd->bi_dram[current_bank - 1].start;
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size = gd->bd->bi_dram[current_bank - 1].size;
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gd->bd->bi_dram[current_bank - 1].start =
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gd->bd->bi_dram[current_bank].start;
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gd->bd->bi_dram[current_bank - 1].size =
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gd->bd->bi_dram[current_bank].size;
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gd->bd->bi_dram[current_bank].start = start;
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gd->bd->bi_dram[current_bank].size = size;
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}
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current_bank--;
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}
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}
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int dram_init_banksize(void)
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{
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sc_rm_mr_t mr;
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sc_faddr_t start, end, end1, end2;
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int i = 0;
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int err;
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end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
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end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
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for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {
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err = get_owned_memreg(mr, &start, &end);
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if (!err) {
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start = roundup(start, MEMSTART_ALIGNMENT);
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if (start > end) /* Small memory region, no use it */
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continue;
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if (start >= PHYS_SDRAM_1 && start <= end1) {
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gd->bd->bi_dram[i].start = start;
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if ((end + 1) <= end1)
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gd->bd->bi_dram[i].size =
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end - start + 1;
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else
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gd->bd->bi_dram[i].size = end1 - start;
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dram_bank_sort(i);
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i++;
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} else if (start >= PHYS_SDRAM_2 && start <= end2) {
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gd->bd->bi_dram[i].start = start;
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if ((end + 1) <= end2)
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gd->bd->bi_dram[i].size =
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end - start + 1;
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else
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gd->bd->bi_dram[i].size = end2 - start;
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dram_bank_sort(i);
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i++;
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}
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}
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}
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/* If error, set to the default value */
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if (!i) {
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
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}
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return 0;
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}
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static u64 get_block_attrs(sc_faddr_t addr_start)
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{
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u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN;
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if ((addr_start >= PHYS_SDRAM_1 &&
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addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) ||
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(addr_start >= PHYS_SDRAM_2 &&
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addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)))
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return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE);
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return attr;
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}
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static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end)
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{
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sc_faddr_t end1, end2;
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end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
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end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
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if (addr_start >= PHYS_SDRAM_1 && addr_start <= end1) {
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if ((addr_end + 1) > end1)
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return end1 - addr_start;
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} else if (addr_start >= PHYS_SDRAM_2 && addr_start <= end2) {
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if ((addr_end + 1) > end2)
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return end2 - addr_start;
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}
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return (addr_end - addr_start + 1);
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}
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#define MAX_PTE_ENTRIES 512
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#define MAX_MEM_MAP_REGIONS 16
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static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS];
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struct mm_region *mem_map = imx8_mem_map;
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void enable_caches(void)
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{
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sc_rm_mr_t mr;
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sc_faddr_t start, end;
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int err, i;
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/* Create map for registers access from 0x1c000000 to 0x80000000*/
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imx8_mem_map[0].virt = 0x1c000000UL;
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imx8_mem_map[0].phys = 0x1c000000UL;
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imx8_mem_map[0].size = 0x64000000UL;
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imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
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i = 1;
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for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) {
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err = get_owned_memreg(mr, &start, &end);
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if (!err) {
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imx8_mem_map[i].virt = start;
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imx8_mem_map[i].phys = start;
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imx8_mem_map[i].size = get_block_size(start, end);
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imx8_mem_map[i].attrs = get_block_attrs(start);
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i++;
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}
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}
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if (i < MAX_MEM_MAP_REGIONS) {
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imx8_mem_map[i].size = 0;
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imx8_mem_map[i].attrs = 0;
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} else {
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puts("Error, need more MEM MAP REGIONS reserved\n");
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icache_enable();
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return;
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}
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for (i = 0; i < MAX_MEM_MAP_REGIONS; i++) {
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debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n",
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i, imx8_mem_map[i].virt, imx8_mem_map[i].phys,
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imx8_mem_map[i].size, imx8_mem_map[i].attrs);
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}
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icache_enable();
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dcache_enable();
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}
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#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
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u64 get_page_table_size(void)
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{
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u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
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u64 size = 0;
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/*
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* For each memory region, the max table size:
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* 2 level 3 tables + 2 level 2 tables + 1 level 1 table
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*/
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size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt;
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/*
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* We need to duplicate our page table once to have an emergency pt to
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* resort to when splitting page tables later on
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*/
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size *= 2;
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/*
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* We may need to split page tables later on if dcache settings change,
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* so reserve up to 4 (random pick) page tables for that.
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*/
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size += one_pt * 4;
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return size;
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}
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#endif
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#if defined(CONFIG_IMX8QM)
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#define FUSE_MAC0_WORD0 452
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#define FUSE_MAC0_WORD1 453
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#define FUSE_MAC1_WORD0 454
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#define FUSE_MAC1_WORD1 455
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#elif defined(CONFIG_IMX8QXP)
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#define FUSE_MAC0_WORD0 708
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#define FUSE_MAC0_WORD1 709
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#define FUSE_MAC1_WORD0 710
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#define FUSE_MAC1_WORD1 711
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#endif
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void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
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{
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u32 word[2], val[2] = {};
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int i, ret;
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if (dev_id == 0) {
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word[0] = FUSE_MAC0_WORD0;
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word[1] = FUSE_MAC0_WORD1;
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} else {
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word[0] = FUSE_MAC1_WORD0;
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word[1] = FUSE_MAC1_WORD1;
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}
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for (i = 0; i < 2; i++) {
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ret = sc_misc_otp_fuse_read(-1, word[i], &val[i]);
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if (ret < 0)
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goto err;
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}
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mac[0] = val[0];
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mac[1] = val[0] >> 8;
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|
mac[2] = val[0] >> 16;
|
|
mac[3] = val[0] >> 24;
|
|
mac[4] = val[1];
|
|
mac[5] = val[1] >> 8;
|
|
|
|
debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
|
|
__func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
|
|
return;
|
|
err:
|
|
printf("%s: fuse %d, err: %d\n", __func__, word[i], ret);
|
|
}
|
|
|
|
u32 get_cpu_rev(void)
|
|
{
|
|
u32 id = 0, rev = 0;
|
|
int ret;
|
|
|
|
ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
|
|
if (ret)
|
|
return 0;
|
|
|
|
rev = (id >> 5) & 0xf;
|
|
id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */
|
|
|
|
return (id << 12) | rev;
|
|
}
|
|
|