mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 02:38:56 +00:00
dd39ee8a54
This delay is already cared by the callers of this function. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
121 lines
2.3 KiB
C
121 lines
2.3 KiB
C
/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include "pll.h"
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/* PLL type: SSC */
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#define SC_PLLCTRL_SSC_DK_MASK GENMASK(14, 0)
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#define SC_PLLCTRL_SSC_EN BIT(31)
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#define SC_PLLCTRL2_NRSTDS BIT(28)
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#define SC_PLLCTRL2_SSC_JK_MASK GENMASK(26, 0)
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/* PLL type: VPLL27 */
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#define SC_VPLL27CTRL_WP BIT(0)
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#define SC_VPLL27CTRL3_K_LD BIT(28)
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/* PLL type: DSPLL */
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#define SC_DSPLLCTRL2_K_LD BIT(28)
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int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
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unsigned int ssc_rate, unsigned int divn)
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{
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void __iomem *base;
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u32 tmp;
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base = ioremap(reg_base, SZ_16);
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if (!base)
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return -ENOMEM;
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if (freq != UNIPHIER_PLL_FREQ_DEFAULT) {
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tmp = readl(base); /* SSCPLLCTRL */
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tmp &= ~SC_PLLCTRL_SSC_DK_MASK;
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tmp |= (487 * freq * ssc_rate / divn / 512) &
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SC_PLLCTRL_SSC_DK_MASK;
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writel(tmp, base);
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tmp = readl(base + 4);
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tmp &= ~SC_PLLCTRL2_SSC_JK_MASK;
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tmp |= (41859 * freq / divn) & SC_PLLCTRL2_SSC_JK_MASK;
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udelay(50);
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}
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tmp = readl(base + 4); /* SSCPLLCTRL2 */
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tmp |= SC_PLLCTRL2_NRSTDS;
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writel(tmp, base + 4);
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iounmap(base);
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return 0;
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}
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int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base)
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{
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void __iomem *base;
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u32 tmp;
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base = ioremap(reg_base, SZ_16);
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if (!base)
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return -ENOMEM;
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tmp = readl(base); /* SSCPLLCTRL */
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tmp |= SC_PLLCTRL_SSC_EN;
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writel(tmp, base);
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iounmap(base);
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return 0;
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}
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int uniphier_ld20_vpll27_init(unsigned long reg_base)
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{
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void __iomem *base;
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u32 tmp;
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base = ioremap(reg_base, SZ_16);
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if (!base)
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return -ENOMEM;
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tmp = readl(base); /* VPLL27CTRL */
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tmp |= SC_VPLL27CTRL_WP; /* write protect off */
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writel(tmp, base);
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tmp = readl(base + 8); /* VPLL27CTRL3 */
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tmp |= SC_VPLL27CTRL3_K_LD;
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writel(tmp, base + 8);
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tmp = readl(base); /* VPLL27CTRL */
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tmp &= ~SC_VPLL27CTRL_WP; /* write protect on */
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writel(tmp, base);
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iounmap(base);
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return 0;
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}
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int uniphier_ld20_dspll_init(unsigned long reg_base)
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{
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void __iomem *base;
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u32 tmp;
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base = ioremap(reg_base, SZ_16);
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if (!base)
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return -ENOMEM;
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tmp = readl(base + 8); /* DSPLLCTRL2 */
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tmp |= SC_DSPLLCTRL2_K_LD;
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writel(tmp, base + 8);
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iounmap(base);
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return 0;
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}
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